546 lines
16 KiB
C
546 lines
16 KiB
C
#ifndef __IDE_rad_H__
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#define __IDE_rad_H__
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/*
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* d_rad.h
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*
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* IDE rad tests header
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*
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* Copyright 1995, Silicon Graphics, Inc.
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* ALL RIGHTS RESERVED
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*
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* UNPUBLISHED -- Rights reserved under the copyright laws of the United
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* States. Use of a copyright notice is precautionary only and does not
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* imply publication or disclosure.
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*
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* U.S. GOVERNMENT RESTRICTED RIGHTS LEGEND:
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* Use, duplication or disclosure by the Government is subject to restrictions
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* as set forth in FAR 52.227.19(c)(2) or subparagraph (c)(1)(ii) of the Rights
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* in Technical Data and Computer Software clause at DFARS 252.227-7013 and/or
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* in similar or successor clauses in the FAR, or the DOD or NASA FAR
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* Supplement. Contractor/manufacturer is Silicon Graphics, Inc.,
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* 2011 N. Shoreline Blvd. Mountain View, CA 94039-7311.
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*
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* THE CONTENT OF THIS WORK CONTAINS CONFIDENTIAL AND PROPRIETARY
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* INFORMATION OF SILICON GRAPHICS, INC. ANY DUPLICATION, MODIFICATION,
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* DISTRIBUTION, OR DISCLOSURE IN ANY FORM, IN WHOLE, OR IN PART, IS STRICTLY
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* PROHIBITED WITHOUT THE PRIOR EXPRESS WRITTEN PERMISSION OF SILICON
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* GRAPHICS, INC.
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*/
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#ident "ide/godzilla/include/d_rad.h: $Revision: 1.1 $"
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#include "d_ioregs.h"
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typedef __uint32_t radregisters_t;
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/*
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* macro definitions: yes, the BR_xxxx_32 Reads and Writes are really 32 bits...
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* register access macros depend bridge_wid_no to be set to
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* the correct xbow port id. Default is XBOW_PORT_F
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* PIO_REG_WR_32(address, mask, value);
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* PIO_REG_RD_32(address, mask, value);
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*/
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/*
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* constants used in rad_regs.c
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*/
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#define RAD_REGS_PATTERN_MAX 6
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#define RAD_CFG_ID_MASK 0xFFFFFFFF
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#define RAD_CFG_ID_DEFAULT 0x0
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#define RAD_CFG_STATUS_MASK 0xFFFFFFFF
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#define RAD_CFG_STATUS_DEFAULT 0x0
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#define RAD_CFG_REV_MASK 0xFFFFFFFF
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#define RAD_CFG_REV_DEFAULT 0x0
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#define RAD_CFG_LATENCY_MASK 0xFFFFFFFF
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#define RAD_CFG_LATENCY_DEFAULT 0x0
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#define RAD_CFG_MEMORY_BASE_MASK 0xFFFFFFFF
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#define RAD_CFG_MEMORY_BASE_DEFAULT 0x0
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#define RAD_PCI_STATUS_MASK 0xFFFFFFFF
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#define RAD_PCI_STATUS_DEFAULT 0x0
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#define RAD_ADAT_RX_MSC_UST_MASK 0xFFFFFFFF
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#define RAD_ADAT_RX_MSC_UST_DEFAULT 0x0
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#define RAD_ADAT_RX_MSC0_SUBMSC_MASK 0xFFFFFFFF
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#define RAD_ADAT_RX_MSC0_SUBMSC_DEFAULT 0x0
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#define RAD_AES_RX_MSC_UST_MASK 0xFFFFFFFF
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#define RAD_AES_RX_MSC_UST_DEFAULT 0x0
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#define RAD_AES_RX_MSC0_SUBMSC_MASK 0xFFFFFFFF
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#define RAD_AES_RX_MSC0_SUBMSC_DEFAULT 0x0
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#define RAD_ATOD_MSC_UST_MASK 0xFFFFFFFF
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#define RAD_ATOD_MSC_UST_DEFAULT 0x0
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#define RAD_ATOD_MSC0_SUBMSC_MASK 0xFFFFFFFF
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#define RAD_ATOD_MSC0_SUBMSC_DEFAULT 0x0
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#define RAD_ADAT_TX_MSC_UST_MASK 0xFFFFFFFF
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#define RAD_ADAT_TX_MSC_UST_DEFAULT 0x0
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#define RAD_ADAT_TX_MSC0_SUBMSC_MASK 0xFFFFFFFF
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#define RAD_ADAT_TX_MSC0_SUBMSC_DEFAULT 0x0
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#define RAD_AES_TX_MSC_UST_MASK 0xFFFFFFFF
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#define RAD_AES_TX_MSC_UST_DEFAULT 0x0
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#define RAD_AES_TX_MSC0_SUBMSC_MASK 0xFFFFFFFF
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#define RAD_AES_TX_MSC0_SUBMSC_DEFAULT 0x0
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#define RAD_DTOA_MSC_UST_MASK 0xFFFFFFFF
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#define RAD_DTOA_MSC_UST_DEFAULT 0x0
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#define RAD_UST_REGISTER_MASK 0xFFFFFFFF
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#define RAD_UST_REGISTER_DEFAULT 0x0
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#define RAD_GPIO_STATUS_MASK 0xFFFFFFFF
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#define RAD_GPIO_STATUS_DEFAULT 0x0
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#define RAD_CHIP_STATUS1_MASK 0xFFFFFFFF
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#define RAD_CHIP_STATUS1_DEFAULT 0x0
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#define RAD_CHIP_STATUS0_MASK 0xFFFFFFFF
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#define RAD_CHIP_STATUS0_DEFAULT 0x0
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#define RAD_UST_CLOCK_CONTROL_MASK 0xFFFFFFFF
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#define RAD_UST_CLOCK_CONTROL_DEFAULT 0x0
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#define RAD_ADAT_RX_CONTROL_MASK 0xFFFFFFFF
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#define RAD_ADAT_RX_CONTROL_DEFAULT 0x0
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#define RAD_AES_RX_CONTROL_MASK 0xFFFFFFFF
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#define RAD_AES_RX_CONTROL_DEFAULT 0x0
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#define RAD_ATOD_CONTROL_MASK 0xFFFFFFFF
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#define RAD_ATOD_CONTROL_DEFAULT 0x0
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#define RAD_ADAT_TX_CONTROL_MASK 0xFFFFFFFF
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#define RAD_ADAT_TX_CONTROL_DEFAULT 0x0
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#define RAD_AES_TX_CONTROL_MASK 0xFFFFFFFF
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#define RAD_AES_TX_CONTROL_DEFAULT 0x0
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#define RAD_DTOA_CONTROL_MASK 0xFFFFFFFF
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#define RAD_DTOA_CONTROL_DEFAULT 0x0
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#define RAD_STATUS_TIMER_MASK 0xFFFFFFFF
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#define RAD_STATUS_TIMER_DEFAULT 0x0
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#define RAD_MISC_CONTROL_MASK 0xFFFFFFFF
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#define RAD_MISC_CONTROL_DEFAULT 0x0
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#define RAD_PCI_HOLDOFF_MASK 0xFFFFFFFF
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#define RAD_PCI_HOLDOFF_DEFAULT 0x0
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#define RAD_PCI_ARB_CONTROL_MASK 0xFFFFFFFF
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#define RAD_PCI_ARB_CONTROL_DEFAULT 0x0
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#define RAD_VOLUME_CONTROL_MASK 0xFFFFFFFF
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#define RAD_VOLUME_CONTROL_DEFAULT 0x0
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#define RAD_RESET_MASK 0xFFFFFFFF
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#define RAD_RESET_DEFAULT 0x0
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#define RAD_GPIO0_MASK 0xFFFFFFFF
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#define RAD_GPIO0_DEFAULT 0x0
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#define RAD_GPIO1_MASK 0xFFFFFFFF
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#define RAD_GPIO1_DEFAULT 0x0
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#define RAD_GPIO2_MASK 0xFFFFFFFF
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#define RAD_GPIO2_DEFAULT 0x0
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#define RAD_GPIO3_MASK 0xFFFFFFFF
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#define RAD_GPIO3_DEFAULT 0x0
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#define RAD_CLOCKGEN_ICTL_MASK 0xFFFFFFFF
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#define RAD_CLOCKGEN_ICTL_DEFAULT 0x0
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#define RAD_CLOCKGEN_REM_MASK 0xFFFFFFFF
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#define RAD_CLOCKGEN_REM_DEFAULT 0x0
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#define RAD_FREQ_SYNTH3_MUX_SEL_MASK 0xFFFFFFFF
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#define RAD_FREQ_SYNTH3_MUX_SEL_DEFAULT 0x0
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#define RAD_FREQ_SYNTH2_MUX_SEL_MASK 0xFFFFFFFF
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#define RAD_FREQ_SYNTH2_MUX_SEL_DEFAULT 0x0
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#define RAD_FREQ_SYNTH1_MUX_SEL_MASK 0xFFFFFFFF
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#define RAD_FREQ_SYNTH1_MUX_SEL_DEFAULT 0x0
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#define RAD_FREQ_SYNTH0_MUX_SEL_MASK 0xFFFFFFFF
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#define RAD_FREQ_SYNTH0_MUX_SEL_DEFAULT 0x0
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#define RAD_MPLL0_LOCK_CONTROL_MASK 0xFFFFFFFF
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#define RAD_MPLL0_LOCK_CONTROL_DEFAULT 0x0
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#define RAD_MPLL1_LOCK_CONTROL_MASK 0xFFFFFFFF
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#define RAD_MPLL1_LOCK_CONTROL_DEFAULT 0x0
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#define RAD_PCI_LOADR_D0_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D0_DEFAULT 0x0
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#define RAD_PCI_HIADR_D0_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D0_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D0_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D0_DEFAULT 0x0
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#define RAD_PCI_LOADR_D1_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D1_DEFAULT 0x0
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#define RAD_PCI_HIADR_D1_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D1_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D1_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D1_DEFAULT 0x0
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#define RAD_PCI_LOADR_D2_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D2_DEFAULT 0x0
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#define RAD_PCI_HIADR_D2_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D2_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D2_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D2_DEFAULT 0x0
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#define RAD_PCI_LOADR_D3_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D3_DEFAULT 0x0
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#define RAD_PCI_HIADR_D3_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D3_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D3_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D3_DEFAULT 0x0
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#define RAD_PCI_LOADR_D4_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D4_DEFAULT 0x0
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#define RAD_PCI_HIADR_D4_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D4_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D4_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D4_DEFAULT 0x0
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#define RAD_PCI_LOADR_D5_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D5_DEFAULT 0x0
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#define RAD_PCI_HIADR_D5_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D5_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D5_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D5_DEFAULT 0x0
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#define RAD_PCI_LOADR_D6_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D6_DEFAULT 0x0
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#define RAD_PCI_HIADR_D6_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D6_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D6_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D6_DEFAULT 0x0
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#define RAD_PCI_LOADR_D7_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D7_DEFAULT 0x0
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#define RAD_PCI_HIADR_D7_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D7_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D7_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D7_DEFAULT 0x0
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#define RAD_PCI_LOADR_D8_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D8_DEFAULT 0x0
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#define RAD_PCI_HIADR_D8_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D8_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D8_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D8_DEFAULT 0x0
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#define RAD_PCI_LOADR_D9_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D9_DEFAULT 0x0
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#define RAD_PCI_HIADR_D9_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D9_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D9_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D9_DEFAULT 0x0
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#define RAD_PCI_LOADR_D10_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D10_DEFAULT 0x0
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#define RAD_PCI_HIADR_D10_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D10_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D10_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D10_DEFAULT 0x0
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#define RAD_PCI_LOADR_D11_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D11_DEFAULT 0x0
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#define RAD_PCI_HIADR_D11_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D11_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D11_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D11_DEFAULT 0x0
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#define RAD_PCI_LOADR_D12_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D12_DEFAULT 0x0
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#define RAD_PCI_HIADR_D12_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D12_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D12_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D12_DEFAULT 0x0
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#define RAD_PCI_LOADR_D13_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D13_DEFAULT 0x0
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#define RAD_PCI_HIADR_D13_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D13_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D13_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D13_DEFAULT 0x0
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#define RAD_PCI_LOADR_D14_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D14_DEFAULT 0x0
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#define RAD_PCI_HIADR_D14_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D14_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D14_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D14_DEFAULT 0x0
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#define RAD_PCI_LOADR_D15_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D15_DEFAULT 0x0
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#define RAD_PCI_HIADR_D15_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D15_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D15_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D15_DEFAULT 0x0
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#define RAD_PCI_LOADR_ADAT_RX_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_ADAT_RX_DEFAULT 0x0
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#define RAD_PCI_CONTROL_ADAT_RX_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_ADAT_RX_DEFAULT 0x0
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#define RAD_PCI_LOADR_AES_RX_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_AES_RX_DEFAULT 0x0
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#define RAD_PCI_CONTROL_AES_RX_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_AES_RX_DEFAULT 0x0
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#define RAD_PCI_LOADR_ATOD_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_ATOD_DEFAULT 0x0
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#define RAD_PCI_CONTROL_ATOD_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_ATOD_DEFAULT 0x0
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#define RAD_PCI_LOADR_ADATSUB_RX_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_ADATSUB_RX_DEFAULT 0x0
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#define RAD_PCI_CONTROL_ADATSUB_RX_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_ADATSUB_RX_DEFAULT 0x0
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#define RAD_PCI_LOADR_AESSUB_RX_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_AESSUB_RX_DEFAULT 0x0
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#define RAD_PCI_CONTROL_AESSUB_RX_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_AESSUB_RX_DEFAULT 0x0
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#define RAD_PCI_LOADR_ADAT_TX_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_ADAT_TX_DEFAULT 0x0
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#define RAD_PCI_CONTROL_ADAT_TX_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_ADAT_TX_DEFAULT 0x0
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#define RAD_PCI_LOADR_AES_TX_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_AES_TX_DEFAULT 0x0
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#define RAD_PCI_CONTROL_AES_TX_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_AES_TX_DEFAULT 0x0
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#define RAD_PCI_LOADR_DTOA_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_DTOA_DEFAULT 0x0
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#define RAD_PCI_CONTROL_DTOA_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_DTOA_DEFAULT 0x0
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#define RAD_PCI_LOADR_STATUS_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_STATUS_DEFAULT 0x0
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#define RAD_PCI_CONTROL_STATUS_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_STATUS_DEFAULT 0x0
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#define RAD_PCI_HIADR_ADAT_RX_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_ADAT_RX_DEFAULT 0x0
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#define RAD_PCI_HIADR_AES_RX_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_AES_RX_DEFAULT 0x0
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#define RAD_PCI_HIADR_ATOD_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_ATOD_DEFAULT 0x0
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#define RAD_PCI_HIADR_ADATSUB_RX_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_ADATSUB_RX_DEFAULT 0x0
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#define RAD_PCI_HIADR_AESSUB_RX_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_AESSUB_RX_DEFAULT 0x0
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#define RAD_PCI_HIADR_ADAT_TX_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_ADAT_TX_DEFAULT 0x0
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#define RAD_PCI_HIADR_AES_TX_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_AES_TX_DEFAULT 0x0
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#define RAD_PCI_HIADR_DTOA_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_DTOA_DEFAULT 0x0
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#define RAD_PCI_HIADR_STATUS_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_STATUS_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U0_0_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U0_0_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U0_1_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U0_1_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U0_2_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U0_2_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U0_3_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U0_3_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U0_4_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U0_4_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U0_5_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U0_5_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U1_0_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U1_0_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U1_1_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U1_1_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U1_2_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U1_2_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U1_3_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U1_3_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U1_4_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U1_4_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U1_5_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U1_5_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U2_0_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U2_0_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U2_1_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U2_1_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U2_2_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U2_2_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U2_3_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U2_3_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U2_4_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U2_4_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U2_5_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U2_5_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U3_0_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U3_0_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U3_1_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U3_1_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U3_2_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U3_2_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U3_3_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U3_3_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U3_4_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U3_4_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U3_5_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U3_5_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXB_U0_0_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXB_U0_0_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_RXA_U0_0_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_RXA_U0_0_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_RXB_U0_0_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_RXB_U0_0_DEFAULT 0x0
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#define RAD_AES_SUBCODE_TXA_LU0_MASK 0xFFFFFFFF
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#define RAD_AES_SUBCODE_TXA_LU0_DEFAULT 0x0
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#define RAD_AES_SUBCODE_TXA_RV2_MASK 0xFFFFFFFF
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#define RAD_AES_SUBCODE_TXA_RV2_DEFAULT 0x0
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#define RAD_AES_SUBCODE_TXB_LU0_MASK 0xFFFFFFFF
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#define RAD_AES_SUBCODE_TXB_LU0_DEFAULT 0x0
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#define RAD_AES_SUBCODE_TXB_RV2_MASK 0xFFFFFFFF
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#define RAD_AES_SUBCODE_TXB_RV2_DEFAULT 0x0
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#define RAD_AES_SUBCODE_RXA_LU0_MASK 0xFFFFFFFF
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#define RAD_AES_SUBCODE_RXA_LU0_DEFAULT 0x0
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#define RAD_AES_SUBCODE_RXA_RV2_MASK 0xFFFFFFFF
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#define RAD_AES_SUBCODE_RXA_RV2_DEFAULT 0x0
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#define RAD_AES_SUBCODE_RXB_LU0_MASK 0xFFFFFFFF
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#define RAD_AES_SUBCODE_RXB_LU0_DEFAULT 0x0
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#define RAD_AES_SUBCODE_RXB_RV2_MASK 0xFFFFFFFF
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#define RAD_AES_SUBCODE_RXB_RV2_DEFAULT 0x0
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#define RAD_ADAT_TX_DATA_MASK 0xFFFFFFFF
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#define RAD_ADAT_TX_DATA_DEFAULT 0x0
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#define RAD_AES_TX_DATA_MASK 0xFFFFFFFF
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#define RAD_AES_TX_DATA_DEFAULT 0x0
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#define RAD_DTOA_DATA_MASK 0xFFFFFFFF
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#define RAD_DTOA_DATA_DEFAULT 0x0
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#define RAD_ADAT_RX_DATA_MASK 0xFFFFFFFF
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#define RAD_ADAT_RX_DATA_DEFAULT 0x0
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#define RAD_AES_RX_DATA_MASK 0xFFFFFFFF
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#define RAD_AES_RX_DATA_DEFAULT 0x0
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#define RAD_ATOD_DATA_MASK 0xFFFFFFFF
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#define RAD_ATOD_DATA_DEFAULT 0x0
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typedef struct _rad_Registers {
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char *name; /* name of the register */
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__uint32_t address; /* address */
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__uint32_t mode; /* read / write only or read & write */
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__uint32_t mask; /* read write mask*/
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__uint32_t def; /* default value */
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} rad_Registers;
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#endif /* __IDE_rad_H__ */
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