93 lines
1.9 KiB
C
Executable File
93 lines
1.9 KiB
C
Executable File
/*
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* fpu/funderflow.c
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*
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*
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*
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* Copyright 1991, Silicon Graphics, Inc.
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* All Rights Reserved.
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*
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* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics, Inc.;
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* the contents of this file may not be disclosed to third parties, copied or
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* duplicated in any form, in whole or in part, without the prior written
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* permission of Silicon Graphics, Inc.
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*
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* RESTRICTED RIGHTS LEGEND:
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* Use, duplication or disclosure by the Government is subject to restrictions
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* as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
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* and Computer Software clause at DFARS 252.227-7013, and/or in similar or
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* successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
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* rights reserved under the Copyright Laws of the United States.
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*/
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#ident "$Revision: 1.3 $"
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/*
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*
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* Floating Point Exerciser - basic functions with simple single
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* underflow
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*
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*/
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#include <sys/param.h>
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#include <sys/cpu.h>
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#include <sys/sbd.h>
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#include <sys/fpu.h>
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#include <fault.h>
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#include <setjmp.h>
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#include "libsk.h"
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#include "libsc.h"
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#include "uif.h"
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static jmp_buf fault_buf;
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#define DIVUND 0x20000
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#define SR_EXCEPT (SR_CU0 | SR_CU1 | SR_IEC | SR_FR | SR_KX)
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extern void UNDERFLOW_OP(void);
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int
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funderflow()
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{
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register int fail;
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register ulong status;
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fail = 0;
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status = GetSR();
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if (setjmp(fault_buf)) {
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if (!(GetFPSR() & DIVUND))
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fail = 1;
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SetFPSR(0);
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} else {
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set_nofault(fault_buf);
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/* clear cause register */
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set_cause(0);
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/* enable cache and fpu - cache ecc errors still enabled */
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SetSR(SR_EXCEPT);
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/* clear the FPSR */
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SetFPSR(0);
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/* set up fpu status register for exception */
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SetFPSR(FP_ENABLE);
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UNDERFLOW_OP();
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DELAY(10);
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/* error if it does not generate an exception */
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fail = 1;
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nofault = 0;
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}
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/* return the status register to original state */
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SetSR(status);
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/* report any error */
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return(fail);
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}
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