calmsacibis995
232 lines
8.9 KiB
Plaintext
232 lines
8.9 KiB
Plaintext
#ident "ide/godzilla/bridge/Plan: $Revision 1.1$"
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Bridge Diagnostics Plan
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=======================
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This document contains the level 1 and level 2 plans for Bridge diagnostics
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in a Godzilla system environment (such as Speed Racer).
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Level 1 Diagnostics Plan
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------------------------
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Assumptions:
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-----------
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- Bridge is connected to Heart directly
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- Heart Level 1 diagnostic tests pass
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- All registers mentioned are Bridge Registers
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- No tests for GIO address mapping
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- No test(s) for SSRAM
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- Prom and serial port are available
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- Only Widget Master tests are done here
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- PCI master tests are done in level 2
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- Every test should do the following at the beginning and end:
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o Program the HEART internal regs to appropriate values, if necessary.
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o Read Bridge Identification register and verify that it has the
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default value. This is just to make sure that we can talk to
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the Bridge chip.
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o Save the Bridge Control Register at the beginning and restore
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at the end.
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o Read Bridge Status register and verify
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o Read INT_STATUS register and make sure that it's zero.
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1) Read/Write Internal Registers
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--------------------------------
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- All read/write registers may be checked with a mask, except the
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Bridge Control Register (This register will be used to check
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the functionality of the Bridge)
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- All read only registers may be read and the value may be reported
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If any of these registers have default value, they may be checked.
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- No write only registers will be tested here (may be used to check
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the functionality of the Bridge)
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2) Internal Memory Tests
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------------------------
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- Perform read/write operations on:
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Internal Address Translation Entry RAM
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Read Response Buffer RAM
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Flash PROMS
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3) Bridge Functionality Tests
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-----------------------------
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- Widget Master Tests -> Crosstalk writes (reads) to (from) PCI:
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We use some of the I/O ports in the serial port PCI device
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to run these tests.
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Using Crosstalk Widget Space to program the PCI device:
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------------------------------------------------------
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1. Select an I/O port (may be a counter on the serial port)
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2. Program INT_MODE register to 0. This ensures that the Bridge
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will not set the ISR on the Heart chip. In the next level of tests,
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we will enable this bit for system level testing. Also, disable
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all the bits in the INT_ENABLE register.
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3. Program PCI/GIO Time out register with reasonable values in
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PCI_RETYR_HLD and PCI_RETRY_CNT fields.
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4. Do the following for X = 0,1,2...,7 (to test device addresses)
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a) If the interrupt pins are connected to the device, program the
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INT_DEV register.
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b) Configure the device (serial port) as device X. This can be done
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by programming the PCI configuration space for device 0.
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c) Read the PCI Configuration Space for DEVICE X and verify.
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d) Program the DEVICE (0) register as follows:
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- Set the DEV_SIZE bit to 0 (to indicate it is a 32 bit device)
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- Set DEV_IO_MEM bit to 0 (to indicate I/O space)
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- Set DEV_OFF bits depending on the I/O address of the port
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e) Write a known value to the selected I/O port. This is done by
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writing the data to the PCI/GIO device 0 address space.
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f) Read Status and INT_STATUS registers to make sure that Bridge is
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idle, and no error is reported.
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g) Read back the data from the selected I/O port. This is done by
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reading the data from the PCI/GIO device 0 address space.
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h) Read Status and INT_STATUS registers to make sure that Bridge is
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idle, and no error is reported.
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5. If there is any memory on the device or if any of the registers
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are memory mapped, repeat the test for those (to test PCI memory)
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Using Crosstalk Larger Mapping Scheme:
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-------------------------------------
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We use the large mapping space to access the serial port. The steps
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are similar to that given in the test above.
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Unused Crosstalk Widget Address Space Test:
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-------------------------------------------
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1. Write to a known value to some of the unused space in the
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Crosstalk Widget Address Space.
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2. Read the INT_STATUS register and verify that INVALID_ADDRESS
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bit is set.
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3. Read PCI/GIO Error Upper (and Lower) Address Register and verify
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that the registers have the expected address.
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4. Repeat the above test for a PIO read operation.
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Interrupt Tests:
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---------------
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This is a system level test, i.e. the HEART and BRIDGE are involved.
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The strategy is to run all of the above mentioned tests, and verify
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if the host (HEART) is interrupted whenever an error occurs.
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In addition to the steps given in the tests above, we do:
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1. Program HOST_ERR_FIELD register. This bit indicates which bit
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location in the host (HEART) interrupt register to test when an
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error occurs.
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2. When an error occurs, read the interrupt status register of
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the host (HEART) and verify that one of the L4_IP bits is set.
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(Programming Note: The code must be modular. The idea is to write
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generic functions that may be shared among these tests)
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Level 2 Diagnostics Plan
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------------------------
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Assumptions:
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-----------
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- Bridge is connected to Heart directly
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- Heart Level 1 diagnostic tests pass
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- Bridge Level 1 diagnostic tests pass
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- All registers mentioned are Bridge Registers
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- No tests for GIO address mapping
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- No test(s) for SSRAM
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- Prom, serial port and SCSI are available
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- PCI master tests are done in this level
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- stand alone SCSI driver is in place
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(dma_write (PCI to Memory) and dma_read (Memory to PCI))
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- 64-bit PCI bus is available
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1) SCSI check out test
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o program the Heart and Bridge registers to values that the scsi driver
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would use
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o perform a simple device check
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o perform the widget master tests for SCSI
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2) PCI Master Tests -> SCSI writes (reads) to (from) Crosstalk
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The following set of tests are written based on SCSI-DMA. Before implementing
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these tests, make sure that the SCSI-DMA and SCSI-setup functions are
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ready and may be called from these tests. In addition, there must be a
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data buffer declared in the main memory for the purpose of SCSI-DMA.
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Note that a PCI master (while Bridge is a slave) can only initiate PCI
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memory access and NOT I/O.
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o 32-bit direct mapping test:-
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- From the physical address of the data buffer, find out the DIR_OFF
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value in the Direct Mapping Register and program the mapping register
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- do a dma_read from a known buffer in memory to SCSI.
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- do a dm_write from SCSI to a scratch buffer in memory
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- compare the buffers for correctness
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- optionally, we could repeat the test by accessing the lower
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1GB PCI Memory space and verify that the Bridge ignored the request
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(do dma_read by using the upper 2GB PCI Memory Space;
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do dma_write by using the lower 1GB PCI Memory Space;
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the contents of the read and write buffers in memory should DIFFER)
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- optionally, we could try a different data buffer and change the
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DIR_OFF value and repeat the test
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(just to make sure that the direct address mapping happens right)
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o 64-bit direct mapping test:-
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- do a dma_read from a known buffer in memory to SCSI.
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- do a dm_write from SCSI to a scratch buffer in memory
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- compare the buffers for correctness
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- optionally, we could repeat the test by accessing the lower
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part of the PCI Memory space and verify that the Bridge ignored
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the request
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(do dma_read by using the upper 256TB PCI Memory Space;
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do dma_write by using the lower 1GB PCI Memory Space;
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the contents of the read and write buffers in memory should DIFFER)
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- optionally, we could try a different data buffer
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(just to make sure that the direct address mapping happens right)
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o page mapped test:-
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- program the Bridge internal RAM with ATE's (Address Translation Entry).
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The ATE may be computed by using the physical address of the data
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buffer in memory and remote map field and attributes
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(use 32-bit addressing range: 4000 0000 - 8000 0000)
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- do a dma_read from a known buffer in memory to SCSI.
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- do a dm_write from SCSI to a scratch buffer in memory
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- compare the buffers for correctness
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- optionally, we could repeat the test by accessing the lower
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1GB PCI Memory space and verify that the Bridge ignored the request
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(do dma_read by using the middle 1GB PCI Memory Space;
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do dma_write by using the lower 1GB PCI Memory Space;
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the contents of the read and write buffers in memory should DIFFER)
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- optionally, we could move the location of the ATE in the RAM
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and repeat the test
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(just to make sure that PMU does the address translation right)
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Open Issues:
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------------
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o How can we test the PCI device attributes such as prefetch, precise, coherent
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and barrier?
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o How can we test all of the read response buffer registers with SCSI and
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serial port connected to Bridge?
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o How can we test the Bridge device arbitration scheme?
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o Do we need to test the byte swapping functionality of Bridge?
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