calmsacibis995
110 lines
4.0 KiB
Plaintext
110 lines
4.0 KiB
Plaintext
#ident "ide/godzilla/ecc/README: $Revision 1.1$"
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ECC testing of Heart-R10k
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=========================
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This file documents the ecc_errgen and ecc_heartecc functions (ecc.c):
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---------- ----------
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| R10k | | Heart |
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| |<------------>| |<------> Memory
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---------- ----------
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The system includes only the microprocessor, the external agent
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(Heart), and memory (part of level1 diags).
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Using the SD/DB_ErrGen bits in HEART:
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====================================
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The tests are implemented by the ecc_errgen function.
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Test 1:
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Hardware tested:
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a) Bad ECC generator from HEART to memory
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b) Single bit ECC reporting in R10k (if such reporting exists)
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Procedure:
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1. set SB_ErrGen in HEART, Enable ECC reporting in R10k
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2. Write memory
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3. read sync register (make sure write gets to memory)
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4. read memory (on read R10k should detect bad ECC)
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5. Inspect Bad Memory Data registers etc.
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Test 2: (similar to test 1)
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Hardware tested:
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a) Bad ECC generator from HEART to memory
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b) Double bit ECC reporting in R10k (if such reporting exists)
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Procedure:
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1. set DB_ErrGen in HEART, Enable ECC reporting in R10k
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2. Write memory
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3. read sync register (make sure write gets to memory)
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4. read memory (on read R10k should detect bad ECC)
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5. Inspect Bad Memory Data registers etc.
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Using the propagation of bad data through the processor (R10000 only):
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======================================================================
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The tests are implemented by the ecc_heartecc function.
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Test 3 is NOT implemented. It is believed that SB error data
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cannot propagate through R10k.
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Test 4 is implemented: it does not use he interrupt but
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polls the exception cause register.
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The "read sync register" function is missing. (XXX)
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Test 3:
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Hardware tested:
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a) ECC checker/detector for processor requests in HEART
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b) Processor single-bit ECC error reporting in HEART
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Procedure:
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1) Put single-bit ECC-error'd data in a R10k register (see below) ***
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2) set GlobalECCen in HEART
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3) set CorSysERE in HEART, unmask approriate bit in HEART mask register
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4) enable ECC reporting in R10k
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5) write bad register to memory location
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(HEART should correct data and capture address)
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6) Wait for CorSysErr Interrupt
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7) service interrupt (includes inspecting PBErrMisc and PBErrSysAddr)
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8) read sync register (make sure write gets to memory)
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9) Read memory
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(on read there should be no error since the data was fixed on write)
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Repeat 1-8 except ...
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3) clear CorSysERE in HEART
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6) Poll CorSysErr bit in HEART Exception cause register
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Two tests for double bit ECC
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Test4: (similar to test 2)
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Hardware tested:
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a) ECC checker/detector for processor requests in HEART
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b) Processor ECC double-bit error reporting in HEART
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Procedure:
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1) Put double-bit ECC-error'd data in a R10k register (see below) ***
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2) set GlobalECCen in HEART
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3) set NCorSysERE in HEART, unmask approriate bit in HEART mask
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register
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4) enable ECC reporting in R10k
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5) write bad register to memory location
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(HEART will discard the data but capture the address correctly)
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6) Wait for NCorSysErr Interrupt
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7) service interrupt (includes inspecting PBErrMisc and PBErrSysAddr)
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8) read sync register (make sure write gets to memory)
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9) Read memory
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(the data should the old memory data since the write was squashed)
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Repeat 1-8 except ...
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3) clear CorSysERE in HEART
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6) Poll CorSysErr bit in HEART Exception cause register
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------------------------------------------------------------
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*** To put bad ECC data in a R10k register
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1) set SB_ErrGen/DB_ErrGen in HEART, clear ECC mode in R10k
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2) Write memory
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3) read sync register
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4) Disable ECC in R10k so it does not correct the read response
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5) read memory. This puts single bit ECC error'd data in R10k register
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6) clear SB_ErrGen /DB_ErrGen in HEART
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