180 lines
6.2 KiB
C
180 lines
6.2 KiB
C
#ifndef __IDE_BRIDGE_H__
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#define __IDE_BRIDGE_H__
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/*
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* d_bridge.h
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*
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* bridge tests header
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*
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* Copyright 1995, Silicon Graphics, Inc.
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* ALL RIGHTS RESERVED
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*
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* UNPUBLISHED -- Rights reserved under the copyright laws of the United
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* States. Use of a copyright notice is precautionary only and does not
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* imply publication or disclosure.
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*
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* U.S. GOVERNMENT RESTRICTED RIGHTS LEGEND:
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* Use, duplication or disclosure by the Government is subject to restrictions
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* as set forth in FAR 52.227.19(c)(2) or subparagraph (c)(1)(ii) of the Rights
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* in Technical Data and Computer Software clause at DFARS 252.227-7013 and/or
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* in similar or successor clauses in the FAR, or the DOD or NASA FAR
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* Supplement. Contractor/manufacturer is Silicon Graphics, Inc.,
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* 2011 N. Shoreline Blvd. Mountain View, CA 94039-7311.
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*
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* THE CONTENT OF THIS WORK CONTAINS CONFIDENTIAL AND PROPRIETARY
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* INFORMATION OF SILICON GRAPHICS, INC. ANY DUPLICATION, MODIFICATION,
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* DISTRIBUTION, OR DISCLOSURE IN ANY FORM, IN WHOLE, OR IN PART, IS STRICTLY
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* PROHIBITED WITHOUT THE PRIOR EXPRESS WRITTEN PERMISSION OF SILICON
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* GRAPHICS, INC.
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*/
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#ident "ide/godzilla/include/d_bridge.h: $Revision: 1.27 $"
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#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
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/*
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* Bridge Ram test contants & macros
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*/
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#define RAM_ADDR_UNIQ 0 /* address uniqueness type of test */
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#define RAM_WALKING 1 /* walking bit type of test */
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#define BRIDGE_EXT_SSRAM_SIZE 0 /* actually determined from ctrl reg */
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/* ram funny addressing : Write Double Words and Read Single Words.
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If a word is written at 0x10000, half is read at 0x10004 (63:32),
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half at 0x11004 (31:0) */
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#define ATE_LSW_OFFSET 0x1000 /* ram ATE Least Significant Word Offset */
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#define ATE_MSW_OFFSET 0x0000 /* ram ATE Most Significant Word Offset */
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#define ATE_RD_OFFSET 0x4 /* ram ATE Read Offset */
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#define LSWORD_ADDR(address) (address+ATE_LSW_OFFSET+ATE_RD_OFFSET)
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#define MSWORD_ADDR(address) (address+ATE_MSW_OFFSET+ATE_RD_OFFSET)
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/*
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* Bridge interrupt test constants (some also used in heart/bridge tests)
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*/
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#define CAUSE_LEVEL0_BIT 0x1<<10 /* position of H level0 intr bit */
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/* in processor cause register */
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/* NOTE: there's 8 interrupt bits in the cause register: */
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/* bits 0 & 1 are for software generated interrupt, */
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/* bits 2-6 are from HEART, bit 7 is from the proc internal timer*/
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#define LEVEL0_LOW 3 /* 0 is IR and 1,2 are flow-control */
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#define LEVEL0_HIGH 15
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#define LEVEL1_LOW 16
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#define LEVEL1_HIGH 31
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#define LEVEL2_LOW 32
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#define LEVEL2_HIGH 49
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#define LEVEL3_LOW 50 /* Timer */
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#define LEVEL3_HIGH 50
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#define LEVEL4_LOW 51
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#define LEVEL4_HIGH 58
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#define LEVEL0 0 /* intr level */
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#define LEVEL1 1
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#define LEVEL2 2
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#define LEVEL3 3
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#define LEVEL4 4
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/*
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* Bridge PCI Master Test constants
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*/
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#define PCI_RETRY_HLD_SHIFT 16 /* depends on the spec */
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#define PCI_RETRY_CNT_SHIFT 0
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#define PCI_RETRY_HLD 0x5
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#define PCI_RETRY_CNT 0x5
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#define PCI_ADD_OFF_MASK 0xfffff
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/*
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* Bridge constants used in the heart-bridge tests
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*/
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#define D_BRIDGE_WID_REQ_TIMEOUT 0x000fffff /* reset value */
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/*
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* Bridge Register Read-Write Masks (32 bits)
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* NOTE: if a bit is undefined at power-up, it is masked
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*/
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#define BRIDGE_WID_ID_MASK 0x0ffff001
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#define BRIDGE_WID_STAT_MASK 0xffff001f
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#define BRIDGE_WID_ERR_UPPER_MASK 0x00000000
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#define BRIDGE_WID_ERR_LOWER_MASK 0x00000000
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#define BRIDGE_WID_CONTROL_MASK 0xffffffff
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#define BRIDGE_WID_REQ_TIMEOUT_MASK 0x000fffff
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#define BRIDGE_WID_INT_UPPER_MASK 0x00000000
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#define BRIDGE_WID_INT_LOWER_MASK 0x00000000
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#define BRIDGE_WID_ERR_CMDWORD_MASK 0x00000000
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#define BRIDGE_WID_LLP_MASK 0x03ffffff
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#define BRIDGE_WID_TFLUSH_MASK 0x00000000
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#define BRIDGE_WID_AUX_ERR_MASK 0x00000000
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#define BRIDGE_WID_RESP_UPPER_MASK 0x0000ffff
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#define BRIDGE_WID_RESP_LOWER_MASK 0xffffffff
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#define BRIDGE_WID_TST_PIN_CTRL_MASK 0x00000fff
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#define BRIDGE_DIR_MAP_MASK 0x00f7ffff
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#define BRIDGE_ARB_MASK 0x0003ff7f
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/* NOTE: the NIC register does not retain the value written in its offset */
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/* field (9:2) but decrements it with time. Hence mask it */
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#define BRIDGE_NIC_MASK 0x000ff002
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#define BRIDGE_PCI_BUS_TIMEOUT_MASK 0x001f13ff
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#define BRIDGE_PCI_CFG_MASK 0x00fff800
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#define BRIDGE_PCI_ERR_UPPER_MASK 0x00000000 /* all unknown at reset */
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#define BRIDGE_PCI_ERR_LOWER_MASK 0x00000000 /* all unknown at reset */
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#define BRIDGE_INT_STATUS_MASK 0xffffffff
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#define BRIDGE_INT_ENABLE_MASK 0x7fffffff
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#define BRIDGE_INT_RST_STAT_MASK 0x0000007f
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#define BRIDGE_INT_MODE_MASK 0x000000ff
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#define BRIDGE_INT_DEVICE_MASK 0x00ffffff
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#define BRIDGE_INT_HOST_ERR_MASK 0x00000000
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#define BRIDGE_INT_ADDR_MASK(x) 0x0003ffff
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#define BRIDGE_DEVICE_MASK(x) 0x19fff000
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#define BRIDGE_WR_REQ_BUF_MASK(x) 0x00000000 /* XXX */
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/*
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* Bridge Register Default Values
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*/
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#define D_BRIDGE_STATUS 0x60
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#define D_GIO_BRIDGE_STATUS 0x40
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/*
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* other constants
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*/
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#define BR_REGS_PATTERN_MAX 6 /* in br_regs */
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#define SUPER_IO_INTR 0x14 /* INTR[4] is on (super-io) */
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/*
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* register access macros depend bridge_wid_no to be set to
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* the correct xbow port id. Default is XBOW_PORT_F
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*/
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#define BR_REG_WR_32(address, mask, value) \
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PIO_REG_WR_32((address+MAIN_WIDGET(bridge_xbow_port)), mask, value);
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#define BR_REG_RD_32(address, mask, value) \
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PIO_REG_RD_32((address+MAIN_WIDGET(bridge_xbow_port)), mask, value);
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/* for Internal ATE: need to to double word writes and single word reads */
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#define BR_ATE_DW_WR_64(address, mask, value) \
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PIO_REG_WR_64((address+MAIN_WIDGET(bridge_xbow_port)), mask, value);
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extern int bridge_xbow_port;
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extern void get_bridge_port(int, char **);
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#define SET_BRIDGE_XBOW_PORT(_argc, _argv) \
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get_bridge_port((_argc), (_argv))
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/*
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* structure definitions
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*/
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typedef struct _Bridge_Regs {
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char *name; /* name of the register */
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__uint64_t address; /* address */
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bridgereg_t mask; /* read-write mask */
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unsigned char mode; /* read / write only or read & write */
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} Bridge_Regs;
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/* used in the bridge ram tests */
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typedef struct _Bridge_Ram {
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char *ram_name; /* name of the ram to be tested */
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__uint64_t start_address; /* start address of ram */
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__uint32_t ram_size; /* ram size in bytes */
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__uint32_t test_type; /* type of ram test to be run */
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} Bridge_Ram;
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#endif /* C || C++ */
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#endif /* __IDE_BRIDGE_H__ */
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