672 lines
20 KiB
C
672 lines
20 KiB
C
/******************************************************************************
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*
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* File: rad.h
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*
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* Description:
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*
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* Defines of offsets to RAD's registers
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*
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* Special Notes:
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*
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*
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* (C) Copyright 1995 by Silicon Graphics, Inc.
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* All Rights Reserved.
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*****************************************************************************/
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/*
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* $Id: d_rad.h,v 1.5 1997/02/20 01:11:01 rattan Exp $
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*/
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#include "sys/RACER/IP30.h"
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/*-----------------------------------------------------------------------------
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*
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* define the RAD's base address
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* (Note: these are only temporary. The forthcoming IO infrastructure will
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* provide a programatic device-indepedent way of obtaining base addresses.)
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*
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*----------------------------------------------------------------------------*/
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#define BYTE_COUNT 0x1f400000 /* specific to GIO2PCI backplane */
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/*
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#define PCI_CFG_BASE RAD_PCI_CFG_BASE
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#define PCI_MEM_BASE RAD_PCI_DEVIO_BASE
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*/
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/*-------------------------------------------------------------------------------
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*
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* RAD config space registers
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*
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*------------------------------------------------------------------------------*/
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#define RAD_CFG_ID (0x00) /* ID reg. */
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#define RAD_CFG_STATUS (0x04) /* status/command reg. */
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#define RAD_CFG_REV (0x08) /* class code/rev reg. */
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#define RAD_CFG_LATENCY (0x0C) /* latency timer reg. */
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#define RAD_CFG_MEMORY_BASE (0x10) /* base address reg. */
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/*-------------------------------------------------------------------------------
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*
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* RAD memory space registers
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*
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*------------------------------------------------------------------------------*/
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/*
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* Misc. Status Registers
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*/
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#define RAD_PCI_STATUS (0x00000000) /* mirror of RAD_CFG_STATUS reg. */
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#define RAD_ADAT_RX_MSC_UST (0x00000004)
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#define RAD_ADAT_RX_MSC0_SUBMSC (0x00000008)
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#define RAD_AES_RX_MSC_UST (0x0000000C)
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#define RAD_AES_RX_MSC0_SUBMSC (0x00000010)
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#define RAD_ATOD_MSC_UST (0x00000014)
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#define RAD_ATOD_MSC0_SUBMSC (0x00000018)
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#define RAD_ADAT_TX_MSC_UST (0x0000001C)
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#define RAD_ADAT_TX_MSC0_SUBMSC (0x00000020)
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#define RAD_AES_TX_MSC_UST (0x00000024)
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#define RAD_AES_TX_MSC0_SUBMSC (0x00000028)
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#define RAD_DTOA_MSC_UST (0x0000002C)
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#define RAD_UST_REGISTER (0x00000030)
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#define RAD_GPIO_STATUS (0x00000034)
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#define RAD_CHIP_STATUS1 (0x00000038)
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#define RAD_CHIP_STATUS0 (0x0000003C)
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/*
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* Control Registers
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*/
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#define RAD_UST_CLOCK_CONTROL (0x00000040)
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#define RAD_ADAT_RX_CONTROL (0x00000044)
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#define RAD_AES_RX_CONTROL (0x00000048)
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#define RAD_ATOD_CONTROL (0x0000004C)
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#define RAD_ADAT_TX_CONTROL (0x00000050)
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#define RAD_AES_TX_CONTROL (0x00000054)
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#define RAD_DTOA_CONTROL (0x00000058)
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#define RAD_STATUS_TIMER (0x0000005C)
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/*
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* PCI Master DMA Control Registers
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*/
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#define RAD_MISC_CONTROL (0x00000070)
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#define RAD_PCI_HOLDOFF (0x00000074)
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#define RAD_PCI_ARB_CONTROL (0x00000078)
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/*
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* Device PIO Indirect Register
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*/
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#define RAD_VOLUME_CONTROL (0x0000007C)
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/*
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* Reset Register
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*/
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#define RAD_RESET (0x00000080)
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/*
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* GPIO Registers
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*/
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#define RAD_GPIO0 (0x00000084)
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#define RAD_GPIO1 (0x00000088)
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#define RAD_GPIO2 (0x0000008C)
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#define RAD_GPIO3 (0x00000090)
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/*
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* Clock Generator Registers
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*/
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#define RAD_CLOCKGEN_ICTL (0x000000A0)
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#define RAD_CLOCKGEN_REM (0x000000A4)
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#define RAD_FREQ_SYNTH3_MUX_SEL (0x000000A8)
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#define RAD_FREQ_SYNTH2_MUX_SEL (0x000000AC)
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#define RAD_FREQ_SYNTH1_MUX_SEL (0x000000B0)
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#define RAD_FREQ_SYNTH0_MUX_SEL (0x000000B4)
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#define RAD_MPLL0_LOCK_CONTROL (0x000000B8)
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#define RAD_MPLL1_LOCK_CONTROL (0x000000BC)
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/*
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* DMA Descriptor RAM START TESTING
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*/
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#define RAD_PCI_LOADR_D0 (0x00000400)
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#define RAD_PCI_HIADR_D0 (0x00000404)
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#define RAD_PCI_CONTROL_D0 (0x00000408)
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#define RAD_PCI_LOADR_D1 (0x0000040C)
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#define RAD_PCI_HIADR_D1 (0x00000410)
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#define RAD_PCI_CONTROL_D1 (0x00000414)
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#define RAD_PCI_LOADR_D2 (0x00000418)
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#define RAD_PCI_HIADR_D2 (0x0000041C)
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#define RAD_PCI_CONTROL_D2 (0x00000420)
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#define RAD_PCI_LOADR_D3 (0x00000424)
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#define RAD_PCI_HIADR_D3 (0x00000428)
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#define RAD_PCI_CONTROL_D3 (0x0000042C)
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#define RAD_PCI_LOADR_D4 (0x00000430)
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#define RAD_PCI_HIADR_D4 (0x00000434)
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#define RAD_PCI_CONTROL_D4 (0x00000438)
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#define RAD_PCI_LOADR_D5 (0x0000043C)
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#define RAD_PCI_HIADR_D5 (0x00000440)
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#define RAD_PCI_CONTROL_D5 (0x00000444)
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#define RAD_PCI_LOADR_D6 (0x00000448)
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#define RAD_PCI_HIADR_D6 (0x0000044C)
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#define RAD_PCI_CONTROL_D6 (0x00000450)
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#define RAD_PCI_LOADR_D7 (0x00000454)
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#define RAD_PCI_HIADR_D7 (0x00000458)
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#define RAD_PCI_CONTROL_D7 (0x0000045C)
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#define RAD_PCI_LOADR_D8 (0x00000460)
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#define RAD_PCI_HIADR_D8 (0x00000464)
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#define RAD_PCI_CONTROL_D8 (0x00000468)
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#define RAD_PCI_LOADR_D9 (0x0000046C)
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#define RAD_PCI_HIADR_D9 (0x00000470)
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#define RAD_PCI_CONTROL_D9 (0x00000474)
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#define RAD_PCI_LOADR_D10 (0x00000478)
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#define RAD_PCI_HIADR_D10 (0x0000047C)
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#define RAD_PCI_CONTROL_D10 (0x00000480)
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#define RAD_PCI_LOADR_D11 (0x00000484)
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#define RAD_PCI_HIADR_D11 (0x00000488)
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#define RAD_PCI_CONTROL_D11 (0x0000048C)
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#define RAD_PCI_LOADR_D12 (0x00000490)
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#define RAD_PCI_HIADR_D12 (0x00000494)
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#define RAD_PCI_CONTROL_D12 (0x00000498)
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#define RAD_PCI_LOADR_D13 (0x0000049C)
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#define RAD_PCI_HIADR_D13 (0x000004A0)
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#define RAD_PCI_CONTROL_D13 (0x000004A4)
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#define RAD_PCI_LOADR_D14 (0x000004A8)
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#define RAD_PCI_HIADR_D14 (0x000004AC)
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#define RAD_PCI_CONTROL_D14 (0x000004B0)
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#define RAD_PCI_LOADR_D15 (0x000004B4)
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#define RAD_PCI_HIADR_D15 (0x000004B8)
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#define RAD_PCI_CONTROL_D15 (0x000004BC)
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/*
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* DMA working registers
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*/
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#define RAD_PCI_LOADR_ADAT_RX (0x000004C0)
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#define RAD_PCI_CONTROL_ADAT_RX (0x000004C4)
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#define RAD_PCI_LOADR_AES_RX (0x000004C8)
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#define RAD_PCI_CONTROL_AES_RX (0x000004CC)
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#define RAD_PCI_LOADR_ATOD (0x000004D0)
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#define RAD_PCI_CONTROL_ATOD (0x000004D4)
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#define RAD_PCI_LOADR_ADATSUB_RX (0x000004D8)
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#define RAD_PCI_CONTROL_ADATSUB_RX (0x000004DC)
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#define RAD_PCI_LOADR_AESSUB_RX (0x000004E0)
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#define RAD_PCI_CONTROL_AESSUB_RX (0x000004E4)
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#define RAD_PCI_LOADR_ADAT_TX (0x000004E8)
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#define RAD_PCI_CONTROL_ADAT_TX (0x000004EC)
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#define RAD_PCI_LOADR_AES_TX (0x000004F0)
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#define RAD_PCI_CONTROL_AES_TX (0x000004F4)
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#define RAD_PCI_LOADR_DTOA (0x000004F8)
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#define RAD_PCI_CONTROL_DTOA (0x000004FC)
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#define RAD_PCI_LOADR_STATUS (0x00000500)
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#define RAD_PCI_CONTROL_STATUS (0x00000504)
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#define RAD_PCI_HIADR_ADAT_RX (0x00000508)
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#define RAD_PCI_HIADR_AES_RX (0x0000050C)
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#define RAD_PCI_HIADR_ATOD (0x00000510)
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#define RAD_PCI_HIADR_ADATSUB_RX (0x00000514)
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#define RAD_PCI_HIADR_AESSUB_RX (0x00000518)
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#define RAD_PCI_HIADR_ADAT_TX (0x0000051C)
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#define RAD_PCI_HIADR_AES_TX (0x00000520)
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#define RAD_PCI_HIADR_DTOA (0x00000524)
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#define RAD_PCI_HIADR_STATUS (0x00000528)
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/*
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* ADAT Subcode Tx A RAM
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* (Note: reading only enabled during RAM test mode.)
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*/
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#define RAD_ADAT_SUBCODE_TXA_U0_0 (0x00001000)
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#define RAD_ADAT_SUBCODE_TXA_U0_1 (0x00001004)
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#define RAD_ADAT_SUBCODE_TXA_U0_2 (0x00001008)
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#define RAD_ADAT_SUBCODE_TXA_U0_3 (0x0000100C)
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#define RAD_ADAT_SUBCODE_TXA_U0_4 (0x00001010)
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#define RAD_ADAT_SUBCODE_TXA_U0_5 (0x00001014)
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#define RAD_ADAT_SUBCODE_TXA_U1_0 (0x00001018)
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#define RAD_ADAT_SUBCODE_TXA_U1_1 (0x0000101C)
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#define RAD_ADAT_SUBCODE_TXA_U1_2 (0x00001020)
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#define RAD_ADAT_SUBCODE_TXA_U1_3 (0x00001024)
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#define RAD_ADAT_SUBCODE_TXA_U1_4 (0x00001028)
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#define RAD_ADAT_SUBCODE_TXA_U1_5 (0x0000102C)
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#define RAD_ADAT_SUBCODE_TXA_U2_0 (0x00001030)
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#define RAD_ADAT_SUBCODE_TXA_U2_1 (0x00001034)
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#define RAD_ADAT_SUBCODE_TXA_U2_2 (0x00001038)
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#define RAD_ADAT_SUBCODE_TXA_U2_3 (0x0000103C)
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#define RAD_ADAT_SUBCODE_TXA_U2_4 (0x00001040)
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#define RAD_ADAT_SUBCODE_TXA_U2_5 (0x00001044)
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#define RAD_ADAT_SUBCODE_TXA_U3_0 (0x00001048)
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#define RAD_ADAT_SUBCODE_TXA_U3_1 (0x0000104C)
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#define RAD_ADAT_SUBCODE_TXA_U3_2 (0x00001050)
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#define RAD_ADAT_SUBCODE_TXA_U3_3 (0x00001054)
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#define RAD_ADAT_SUBCODE_TXA_U3_4 (0x00001058)
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#define RAD_ADAT_SUBCODE_TXA_U3_5 (0x0000105C)
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/*
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* ADAT Subcode Tx B RAM
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* (Note: reading only enabled during RAM test mode.)
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*/
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#define RAD_ADAT_SUBCODE_TXB_U0_0 (0x00001080)
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/*
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* ADAT Subcode Rx A RAM
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* (Note: reading only enabled during RAM test mode.)
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*/
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#define RAD_ADAT_SUBCODE_RXA_U0_0 (0x00001800)
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/*
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* ADAT Subcode Rx B RAM
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* (Note: reading only enabled during RAM test mode.)
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*/
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#define RAD_ADAT_SUBCODE_RXB_U0_0 (0x00001880)
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/*
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* AES Subcode Tx A RAM
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* (Note: reading only enabled during RAM test mode.)
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*/
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#define RAD_AES_SUBCODE_TXA_LU0 (0x00001100)
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#define RAD_AES_SUBCODE_TXA_RV2 (0x00001200)
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/*
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* AES Subcode Tx B RAM
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* (Note: reading only enabled during RAM test mode.)
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*/
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#define RAD_AES_SUBCODE_TXB_LU0 (0x00001180)
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#define RAD_AES_SUBCODE_TXB_RV2 (0x00001210)
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/*
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* AES Subcode Rx A RAM
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* (Note: reading only enabled during RAM test mode.)
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*/
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#define RAD_AES_SUBCODE_RXA_LU0 (0x00001900)
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#define RAD_AES_SUBCODE_RXA_RV2 (0x00001A00)
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/*
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* AES Subcode Rx B RAM
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* (Note: reading only enabled during RAM test mode.)
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*/
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#define RAD_AES_SUBCODE_RXB_LU0 (0x00001980)
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#define RAD_AES_SUBCODE_RXB_RV2 (0x00001A10)
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/*
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* Tx RAM
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* (Note: reading and writing only enabled during RAM test mode.)
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*/
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#define RAD_ADAT_TX_DATA (0x00001400)
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#define RAD_AES_TX_DATA (0x00001600)
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#define RAD_DTOA_DATA (0x00001700)
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/*
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* Rx RAM
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* (Note: reading and writing only enabled during RAM test mode.)
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*/
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#define RAD_ADAT_RX_DATA (0x00001C00)
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#define RAD_AES_RX_DATA (0x00001E00)
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#define RAD_ATOD_DATA (0x00001F00)
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/*Register test stuff*/
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#define RAD_PCI_LOADR_D0_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D0_DEFAULT 0x0
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#define RAD_PCI_HIADR_D0_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D0_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D0_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D0_DEFAULT 0x0
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#define RAD_PCI_LOADR_D1_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D1_DEFAULT 0x0
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#define RAD_PCI_HIADR_D1_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D1_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D1_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D1_DEFAULT 0x0
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#define RAD_PCI_LOADR_D2_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D2_DEFAULT 0x0
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#define RAD_PCI_HIADR_D2_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D2_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D2_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D2_DEFAULT 0x0
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#define RAD_PCI_LOADR_D3_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D3_DEFAULT 0x0
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#define RAD_PCI_HIADR_D3_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D3_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D3_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D3_DEFAULT 0x0
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#define RAD_PCI_LOADR_D4_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D4_DEFAULT 0x0
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#define RAD_PCI_HIADR_D4_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D4_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D4_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D4_DEFAULT 0x0
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#define RAD_PCI_LOADR_D5_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D5_DEFAULT 0x0
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#define RAD_PCI_HIADR_D5_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D5_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D5_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D5_DEFAULT 0x0
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#define RAD_PCI_LOADR_D6_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D6_DEFAULT 0x0
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#define RAD_PCI_HIADR_D6_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D6_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D6_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D6_DEFAULT 0x0
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#define RAD_PCI_LOADR_D7_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D7_DEFAULT 0x0
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#define RAD_PCI_HIADR_D7_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D7_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D7_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D7_DEFAULT 0x0
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#define RAD_PCI_LOADR_D8_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D8_DEFAULT 0x0
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#define RAD_PCI_HIADR_D8_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D8_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D8_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D8_DEFAULT 0x0
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#define RAD_PCI_LOADR_D9_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D9_DEFAULT 0x0
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#define RAD_PCI_HIADR_D9_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D9_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D9_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D9_DEFAULT 0x0
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#define RAD_PCI_LOADR_D10_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D10_DEFAULT 0x0
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#define RAD_PCI_HIADR_D10_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D10_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D10_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D10_DEFAULT 0x0
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#define RAD_PCI_LOADR_D11_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D11_DEFAULT 0x0
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#define RAD_PCI_HIADR_D11_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D11_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D11_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D11_DEFAULT 0x0
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#define RAD_PCI_LOADR_D12_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D12_DEFAULT 0x0
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#define RAD_PCI_HIADR_D12_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D12_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D12_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D12_DEFAULT 0x0
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#define RAD_PCI_LOADR_D13_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D13_DEFAULT 0x0
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#define RAD_PCI_HIADR_D13_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D13_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D13_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D13_DEFAULT 0x0
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#define RAD_PCI_LOADR_D14_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D14_DEFAULT 0x0
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#define RAD_PCI_HIADR_D14_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D14_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D14_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D14_DEFAULT 0x0
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#define RAD_PCI_LOADR_D15_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_D15_DEFAULT 0x0
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#define RAD_PCI_HIADR_D15_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_D15_DEFAULT 0x0
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#define RAD_PCI_CONTROL_D15_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_D15_DEFAULT 0x0
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#define RAD_PCI_LOADR_ADAT_RX_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_ADAT_RX_DEFAULT 0x0
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#define RAD_PCI_CONTROL_ADAT_RX_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_ADAT_RX_DEFAULT 0x0
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#define RAD_PCI_LOADR_AES_RX_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_AES_RX_DEFAULT 0x0
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#define RAD_PCI_CONTROL_AES_RX_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_AES_RX_DEFAULT 0x0
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#define RAD_PCI_LOADR_ATOD_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_ATOD_DEFAULT 0x0
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#define RAD_PCI_CONTROL_ATOD_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_ATOD_DEFAULT 0x0
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#define RAD_PCI_LOADR_ADATSUB_RX_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_ADATSUB_RX_DEFAULT 0x0
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#define RAD_PCI_CONTROL_ADATSUB_RX_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_ADATSUB_RX_DEFAULT 0x0
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#define RAD_PCI_LOADR_AESSUB_RX_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_AESSUB_RX_DEFAULT 0x0
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#define RAD_PCI_CONTROL_AESSUB_RX_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_AESSUB_RX_DEFAULT 0x0
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#define RAD_PCI_LOADR_ADAT_TX_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_ADAT_TX_DEFAULT 0x0
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#define RAD_PCI_CONTROL_ADAT_TX_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_ADAT_TX_DEFAULT 0x0
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#define RAD_PCI_LOADR_AES_TX_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_AES_TX_DEFAULT 0x0
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#define RAD_PCI_CONTROL_AES_TX_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_AES_TX_DEFAULT 0x0
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#define RAD_PCI_LOADR_DTOA_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_DTOA_DEFAULT 0x0
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#define RAD_PCI_CONTROL_DTOA_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_DTOA_DEFAULT 0x0
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#define RAD_PCI_LOADR_STATUS_MASK 0xFFFFFFFF
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#define RAD_PCI_LOADR_STATUS_DEFAULT 0x0
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#define RAD_PCI_CONTROL_STATUS_MASK 0xFFFFFFFF
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#define RAD_PCI_CONTROL_STATUS_DEFAULT 0x0
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#define RAD_PCI_HIADR_ADAT_RX_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_ADAT_RX_DEFAULT 0x0
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#define RAD_PCI_HIADR_AES_RX_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_AES_RX_DEFAULT 0x0
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#define RAD_PCI_HIADR_ATOD_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_ATOD_DEFAULT 0x0
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#define RAD_PCI_HIADR_ADATSUB_RX_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_ADATSUB_RX_DEFAULT 0x0
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#define RAD_PCI_HIADR_AESSUB_RX_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_AESSUB_RX_DEFAULT 0x0
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#define RAD_PCI_HIADR_ADAT_TX_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_ADAT_TX_DEFAULT 0x0
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#define RAD_PCI_HIADR_AES_TX_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_AES_TX_DEFAULT 0x0
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#define RAD_PCI_HIADR_DTOA_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_DTOA_DEFAULT 0x0
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#define RAD_PCI_HIADR_STATUS_MASK 0xFFFFFFFF
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#define RAD_PCI_HIADR_STATUS_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U0_0_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U0_0_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U0_1_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U0_1_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U0_2_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U0_2_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U0_3_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U0_3_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U0_4_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U0_4_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U0_5_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U0_5_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U1_0_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U1_0_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U1_1_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U1_1_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U1_2_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U1_2_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U1_3_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U1_3_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U1_4_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U1_4_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U1_5_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U1_5_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U2_0_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U2_0_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U2_1_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U2_1_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U2_2_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U2_2_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U2_3_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U2_3_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U2_4_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U2_4_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U2_5_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U2_5_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U3_0_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U3_0_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U3_1_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U3_1_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U3_2_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U3_2_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U3_3_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U3_3_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U3_4_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U3_4_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXA_U3_5_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXA_U3_5_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_TXB_U0_0_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_TXB_U0_0_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_RXA_U0_0_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_RXA_U0_0_DEFAULT 0x0
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#define RAD_ADAT_SUBCODE_RXB_U0_0_MASK 0xFFFFFFFF
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#define RAD_ADAT_SUBCODE_RXB_U0_0_DEFAULT 0x0
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#define RAD_AES_SUBCODE_TXA_LU0_MASK 0xFFFFFFFF
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#define RAD_AES_SUBCODE_TXA_LU0_DEFAULT 0x0
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#define RAD_AES_SUBCODE_TXA_RV2_MASK 0xFFFFFFFF
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#define RAD_AES_SUBCODE_TXA_RV2_DEFAULT 0x0
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#define RAD_AES_SUBCODE_TXB_LU0_MASK 0xFFFFFFFF
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#define RAD_AES_SUBCODE_TXB_LU0_DEFAULT 0x0
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#define RAD_AES_SUBCODE_TXB_RV2_MASK 0xFFFFFFFF
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#define RAD_AES_SUBCODE_TXB_RV2_DEFAULT 0x0
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#define RAD_AES_SUBCODE_RXA_LU0_MASK 0xFFFFFFFF
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#define RAD_AES_SUBCODE_RXA_LU0_DEFAULT 0x0
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#define RAD_AES_SUBCODE_RXA_RV2_MASK 0xFFFFFFFF
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#define RAD_AES_SUBCODE_RXA_RV2_DEFAULT 0x0
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#define RAD_AES_SUBCODE_RXB_LU0_MASK 0xFFFFFFFF
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#define RAD_AES_SUBCODE_RXB_LU0_DEFAULT 0x0
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#define RAD_AES_SUBCODE_RXB_RV2_MASK 0xFFFFFFFF
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#define RAD_AES_SUBCODE_RXB_RV2_DEFAULT 0x0
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#define RAD_ADAT_TX_DATA_MASK 0xFFFFFFFF
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#define RAD_ADAT_TX_DATA_DEFAULT 0x0
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#define RAD_AES_TX_DATA_MASK 0xFFFFFFFF
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#define RAD_AES_TX_DATA_DEFAULT 0x0
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#define RAD_DTOA_DATA_MASK 0xFFFFFFFF
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#define RAD_DTOA_DATA_DEFAULT 0x0
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#define RAD_ADAT_RX_DATA_MASK 0xFFFFFFFF
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#define RAD_ADAT_RX_DATA_DEFAULT 0x0
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#define RAD_AES_RX_DATA_MASK 0xFFFFFFFF
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#define RAD_AES_RX_DATA_DEFAULT 0x0
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#define RAD_ATOD_DATA_MASK 0xFFFFFFFF
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#define RAD_ATOD_DATA_DEFAULT 0x0
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#define RADREGS_REGS_PATTERN_MAX 6
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#define SHOE_BRIDGE_BASE 0x1d000000
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