134 lines
3.2 KiB
C
134 lines
3.2 KiB
C
#if !defined(__PIO_H__)
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#define __PIO_H__
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/* The following addresses are unmapped and uncached */
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#define PLP_BASE 0xBF380000 /* Point at ls byte */
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#define ALT_PLP_BASE 0xBF388000 /* Point at ls byte */
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/* Valid for all modes, except ECP */
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#ifdef notdef
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#define PLP_DATA (*(volatile unsigned char*)(PLP_BASE))
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#else /* notdef */
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#define PLP_DATA_ADDR ((volatile unsigned char*)(PLP_BASE))
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#define PLP_DATA (READ_REG64(PLP_DATA_ADDR, long long))
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#define SET_PLP_DATA(data) (WRITE_REG64(data,PLP_DATA_ADDR, long long))
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#endif /* notdef */
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/* Valid for ECP mode only */
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#ifdef notdef
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#define ECP_ADDR_FIFO (*(volatile unsigned char*)(PLP_BASE))
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#endif /* notdef */
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/* Parallel Port Status Register, valid for all modes */
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#define PLP_STATUS (*(volatile long long*) (PLP_BASE + 0x100))
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#define PLP_BUSY 0x80
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#define PLP_ACK 0x40
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#define PLP_PE 0x20
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#define PLP_SLCT 0x10
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#define PLP_ERR 0x08
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#define PLP_PRINT 0x04
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#define PLP_WRITE_FIFO 0x02 /* For testing only, actually rsvd */
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#define PLP_READ_FIFO 0x01 /* For testing only, actually rsvd */
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/* Parallel Port Control Register, valid for all modes */
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#ifdef notdef
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#define PLP_CONTROL (*(volatile unsigned char*)(PLP_BASE + 0x200))
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#else /* notdef */
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#define PLP_CONTROL_ADDR ((volatile unsigned char*)(PLP_BASE + 0x200))
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#define PLP_CONTROL (READ_REG64(PLP_CONTROL_ADDR,long long))
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#define SET_PLP_CONTROL(data) (WRITE_REG64(data,PLP_CONTROL_ADDR,long long))
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#endif /* notdef */
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#define PLP_DIR 0x20
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#define PLP_INT2EN 0x10
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#define PLP_SLIN 0x08
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#define PLP_INIT 0x04
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#define PLP_AFD 0x02
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#define PLP_STB 0x01
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#ifdef notdef
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/* Valid for EPP mode only */
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#define EPP_ADDRESS (*(volatile unsigned char*)(PLP_BASE + 0x300))
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#define EPP_DATA (*(volatile unsigned char*)(PLP_BASE + 0x400))
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/* Valid for ECP mode only */
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#define ECP_DATA_FIFO (*(volatile unsigned char*)(ALT_PLP_BASE))
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/* Valid for Configuration mode only */
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#define PLP_CFNG_A (*(volatile unsigned char*)(ALT_PLP_BASE))
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#define PLP_CFNG_B (*(volatile unsigned char*)(ALT_PLP_BASE + 0x100))
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#endif /* notdef */
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/* Parallel Port Extended Control Register */
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#ifdef notdef
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#define PLP_EXT_CNTRL (*(volatile unsigned char*)(ALT_PLP_BASE + 0x200))
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#else /* notdef */
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#define PLP_EXT_CNTRL_ADDR ((volatile unsigned char*)(ALT_PLP_BASE + 0x200))
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#define PLP_EXT_CNTRL (READ_REG64(PLP_EXT_CNTRL_ADDR, long long))
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#define SET_PLP_EXT_CNTRL(data) (WRITE_REG64(data,PLP_EXT_CNTRL_ADDR,long long))
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#endif /* notdef */
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#define PLP_MODE (PLP_EXT_CNTRL >> 5)
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#define PLP_SET_MODE(m) PLP_EXT_CNTRL=(PLP_EXT_CNTRL|((m&7)<<5))
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#ifdef notdef
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#define PLP_STD_MODE 0x0
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#define PLP_BI_DIR_MODE 0x1
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#define PLP_FIFO_MODE 0x2
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#define PLP_ECP_MODE 0x3
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#define PLP_EPP_MODE 0x4
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#define PLP_TEST_MODE 0x6
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#define PLP_CNFG_MODE 0x7
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#else /*notdef */
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#define PLP_STD_MODE 0x00
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#define PLP_BI_DIR_MODE 0x20
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#define PLP_FIFO_MODE 0x40
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#define PLP_ECP_MODE 0x60
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#define PLP_EPP_MODE 0x80
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#define PLP_TEST_MODE 0xc0
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#define PLP_CNFG_MODE 0xe0
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#endif /*notdef*/
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#define PLP_NERR_INTR 0x10
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#define PLP_DMA_EN 0x08
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#define PLP_SERV_INTR 0x04
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#define PLP_FULL 0x02
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#define PLP_EMPTY 0x01
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#endif
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