#ident "ide/godzilla/mem/README file: Revision: 1.1 $"
Speedracer memory tests
=======================
Summary
-------
The IP30 (Speedracer) Memory Diagnostics will include a combination
of pon (power-on) tests, and standalone (ide) tests.
This doc covers the standalone (ide) tests only.
Overview of the existing memory tests (IP22 and IP26): state as of 4-9-95
=========================================================================
The following tests are in the stand tree, in ide/fforward/mem
(for IP22 and IP26).
One must note that IP22 has a parity checking feature, IP26, an ECC
(Error Correcting Code) feature.
- memtest.c contains the basic memory test (address uniqueness and
walking bit tests)
- memtest2.c gives access to over a dozen memory tests,
including the basic memory tests, via a test number.
It is also called expanded memory test.
The tests have different coverages and lengths, using different algorithms.
A couple of them (tb_test and checker) seem to be used
exclusively by manufacturing.
- separate memory tests: low_memtest (including parity, for IP22)
dram_diagnostics (including parity, for IP22)
dram2_diagnostics
khlow_dr
blk_test
shift_dram
- memory diagram feature. The function is print_memory_diagram in diagram.c.
- parity tests (IP22 only): dcache_par
icache_par
parity_test
pargenlog_test
Test durations:
---------------
These were measured on an IP26/640MB system (teton9):
addruniq 3 min
march 2 hours
mats 4 min
kn 5 min
altaccess 45 min
khpar N/A for IP26
movi days
walkingbit 3 hours
marchX 5 min
marchY 5 min
butterfly 4 min
hardware dependencies
=====================
The hardware dependencies are few: they are limited mostly to
controlling the parity/ECC bits in the memory controller
(CPUCTRL0 for IP22/26, HEART_MODE for IP30) and to flushing
(or not) the D-cache.
There is also an issue with reporting errors (HEART and MC are different).
Proposal of guidelines for reorganization
=========================================
The primary objective is to have a set of tests for bring-up,
then to package a minimal set that is fully debugged.
- bundle the memory tests into 4 functional groups: Low DRAM, memory,
ECC, and manufacturing memory tests
- create a separate "memtest2"-type of menu for Mfg
- keep the memory diagram separate
- port most IP22/IP26 tests and provide an entry for each one in the
appropriate "bundle"; as each test is tested and debugged,
I will evaluate which are for keeps.
- remove memtest which runs addruniq and walkingbit successively
(these tests are already in memtest2). Rename metest2 memtest.
- for the field, a selection of tests will be put together to achieve
a couple of coverage/length combinations.
- move and create all header files in IP30/include and godzilla/include,
that both engr and mfg can share.
New organization
================
The following memory test commands will be offered in cpu_diagcmds:
- ldram remains the low DRAM (0-16MB) data/address test
(low_memtest/ldramtest.c&ldram_diags.s)
- dram remains the dram diagnostics (dram_diagnostics/dram_diag.c)
- dram2 remains the expanded dram diagnostics (applicable to speedracer??)
- memtest <testnumber> where the existing numbering is preserved:
<test number> = test title (function/filename)
0 = memory address uniqueness (memaddruniq/addruniq.c)
1 = marching ones and zeroes (March_l/march.c)
2 = modified algorithmic test sequence memory test (Mats_l/mats.c)
3 = Knaizuk-Hartman memory test (Kh_l/kh.c)
4 = alternating access test (Altaccess_l/altaccess.c)
5 = Knaizuk-Hartman test of the D-cache (khparity/khparity.s) (??)
6 = moving inversions memory test (Movi_l/movi.c)
7 = walking bit test (memwalkingbit/walkingbit.c)
8 = marchX test (marchX/marchxy.c)
9 = marchY test (marchY/marchxy.c)
10 = three bit test (three_l/threebit.c&misc.s)
11 = butterfly test (Butterfly_l/butterfly.c)
12 = Knaizuk-Hartman double word test (khdouble_drv/khdouble.c)
13 = new three bit test (three_ll/new3bit.c&misc.s)
(*NEW*) 14 = block read/write test (blk_test/blk.c)
(was blk) (XXX remove?)
(*NEW*) 15 = Shifting data patterns into successive addresses
(was shift) (shift_dram/shift_dram.c)(XXX remove?)
- ecc_test, testing the IP30 ECC feature (*ALL NEW*)
- help_mem still prints the memory diagram
- all mfg tests could be listed under a mfg_diagcmds table and
located in IP30/mfg.
The mfg memory tests could be kept together in a memtest-like function,
something like:
mfgmtest <testnumber>
<test number> = test title (function/filename)
0 = tb_test (used to be a memtest2 option)
1 = checker (used to be a memtest2 option)
- all csd test could be listed under the (existing) field_diagcmds
where there could be a csdmtest command for memory tests.
These memory tests would select a set of memory test to achieve a
variety of coverage and test time lengths.
The "packaging" (gui, selection of tests etc.) could reside in
an IP30/csd directory.
NOTE: this covers only the memory CSD tests.
0 = short test (<1 min) for approx XX% coverage
1 = medium test (few minutes) for approx XX% coverage
2 = long test (10 min ???) for approx XX% coverage
The individual files have comments at the top explaining what was done
specifically when ported to Speedracer, plus what is still undefined
or in question.
what's left to do
=================
Each file has a "to do" list.
- review each file for XXX's and "to do" list.
- bring-up memory tests on emulator: length will be an issue
- come-up with a "fast" test
- revise the code pointing at a SIMM number
