462 lines
10 KiB
C
462 lines
10 KiB
C
/*********************************************************************
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* *
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* Tite : RadRamTest *
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* Author: Jimmy Acosta *
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* Date : 03.18.96 *
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* *
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*********************************************************************
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* *
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* Description: *
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* *
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* This program tests reading and writing into RAD's RAM. It *
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* will verify that the saturation and sign extension is properly *
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* working. *
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* Options: *
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* -v (verbose mode) *
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* -r (Reset RAD after operation) *
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* *
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* (C) Copyright 1996 by Silicon Graphics, Inc. *
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* All Rights Reserved. *
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*********************************************************************/
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#include "ide_msg.h"
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#include "uif.h"
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#include "sys/types.h"
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#include <sgidefs.h>
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#include "sys/sbd.h"
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#include "libsc.h"
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#include "sys/PCI/bridge.h"
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#include "d_godzilla.h"
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#include "d_prototypes.h"
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#include "d_frus.h"
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#include "d_rad_util.h"
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#include "d_rad.h"
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#define RAD_POSITIVE_SAT 0x800000
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#define RAD_NEGATIVE_SAT 0x7FFFFF
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#define RAD_NUMBER_ADAT_SUBCODE 24
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#define RAD_NUMBER_AES_SUBCODE1 32
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#define RAD_NUMBER_AES_SUBCODE2 4
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#define RAD_NUMBER_DATA 256
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typedef enum { NONE,
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POSITIVE_SATURATION,
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NEGATIVE_SATURATION,
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SIGN_EXTENSION } RadTestType;
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static int verbose=0;
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int RadRWVPattern(uint_t , uint_t , int );
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int RadRamTest(int argc, char** argv)
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{
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int status = 0, globStatus=0;
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int i, bad_arg;
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int value = 0;
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int pattern = 0x55AA00;
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int positiveSaturation = 0x01AABB00;
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int negativeSaturation = 0x81AABB00;
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int signExtension = 0x80AA00;
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if (IsOctaneLx())
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return 100;
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RadConfigBase = RAD_PCI_CFG_BASE; /*default*/
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RadMemoryBase = RAD_PCI_DEVIO_BASE; /*default*/
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/*check args*/
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if (argc > 1) {
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if ( !(strcmp(argv[1], "-s0")) || !(strcmp(argv[1], "-s1"))
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|| !(strcmp(argv[1], "-s2")) || !(strcmp(argv[1], "-s3"))
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) {}
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else {
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msg_printf(INFO, "PCI Slot argument required\n");
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msg_printf(INFO, "Usage: rad_ram -s[0..2]\n");
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return 1; /*non fatal fail*/
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}
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}
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/* get the args */
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argc--; argv++;
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while (argc && argv[0][0]=='-' && argv[0][1]!='\0') {
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switch (argv[0][1]) {
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case 's':
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switch (argv[0][2]) {
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case '0':
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RadConfigBase = SHOE_BRIDGE_BASE | 0x020000;
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RadMemoryBase = SHOE_BRIDGE_BASE | 0x200000;
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break;
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case '1':
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RadConfigBase = SHOE_BRIDGE_BASE | 0x021000;
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RadMemoryBase = SHOE_BRIDGE_BASE | 0x400000;
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break;
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case '2':
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RadConfigBase = SHOE_BRIDGE_BASE | 0x022000;
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RadMemoryBase = SHOE_BRIDGE_BASE | 0x600000;
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break;
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case '3':
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RadConfigBase = SHOE_BRIDGE_BASE | 0x023000;
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RadMemoryBase = SHOE_BRIDGE_BASE | 0x700000;
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break;
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default:
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return 1;
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}
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break;
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default:
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bad_arg++; break;
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}
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argc--; argv++;
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}
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msg_printf(INFO, "Testing RAD RAM at CONF Addr 0x%x, MEM Addr 0x%x\n", RadConfigBase, RadMemoryBase);
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/*turned off to match arg passing in IDE
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verbose = 0;
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for(i=1; i<argc; i++) {
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if(!strcmp("-r",argv[i]))
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if(!strcmp("-v",argv[i]))
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verbose = 1;
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if(!strcmp("-p",argv[i]))
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pattern = atoi(argv[++i]);
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}
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*/
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/*remove these settings if -v -p turned on*/
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verbose = 1;
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pattern = 0;
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/*
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* Initialize and verify RAD configuration registers.
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*/
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msg_printf(DBG,"RAD Configuration \n");
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/* causes exception while RAD_WRITE, READ OK*/
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status = RadSetup();
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if(status == -1) {
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msg_printf(DBG,"Problems setting up RAD, exiting diagnostic\n");
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return -1;
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}
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/*
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* Set RAD into RAM test mode
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*/
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msg_printf(DBG,"Set RAD into RAM test mode\n");
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SETBITS(value,0x1,1,5);
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RAD_WRITE(RAD_MISC_CONTROL,value);
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/*PIO_REG_WR_32(PCI_MEM_BASE+RAD_MISC_CONTROL, mask32, value);*/
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/*
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* We will test all RAD DMA areas: DMA RAM, Tx Subcode RAM, Tx Data RAM,
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* Rx Subcode RAM, Rx Data RAM. For the data RAM test saturation and
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* sign extension.
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*/
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/* Start out with Descriptor RAM */
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msg_printf(DBG,"Testing Descriptor RAM\n");
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status = RadRWVPattern(RAD_PCI_LOADR_D0,
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RAD_NUMBER_DESCRIPTORS,
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pattern);
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if(verbose) {
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msg_printf(DBG,"RAD DMA Descriptor Ram R/W test: ");
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if(status)
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msg_printf(DBG,"FAIL\n");
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else
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msg_printf(DBG,"OK\n");
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}
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globStatus |= status;
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status = 0;
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/* Test RAD DMA Working registers */
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status = RadRWVPattern(RAD_PCI_LOADR_ADAT_RX,
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RAD_NUMBER_WORK_REGISTERS,
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pattern);
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if(verbose) {
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msg_printf(DBG,"RAD DMA Working Registers R/W test: ");
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if(status)
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msg_printf(DBG,"FAIL\n");
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else
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msg_printf(DBG,"OK\n");
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}
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globStatus |= status;
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status = 0;
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/* Test Subcode Ram */
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status = RadRWVPattern(RAD_ADAT_SUBCODE_TXA_U0_0,
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RAD_NUMBER_ADAT_SUBCODE,
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pattern);
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if(verbose) {
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msg_printf(DBG,"RAD ADAT Subcode Tx A Ram R/W test: ");
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if(status)
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msg_printf(DBG,"FAIL\n");
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else
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msg_printf(DBG,"OK\n");
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}
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globStatus |= status;
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status = 0;
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status = RadRWVPattern(RAD_ADAT_SUBCODE_TXB_U0_0,
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RAD_NUMBER_ADAT_SUBCODE,
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pattern);
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if(verbose) {
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msg_printf(DBG,"RAD ADAT Subcode Tx B Ram R/W test: ");
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if(status)
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msg_printf(DBG,"FAIL\n");
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else
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msg_printf(DBG,"OK\n");
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}
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globStatus |= status;
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status = 0;
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/*
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* AES Subcode has a break in the address due to
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* size requirements in the standard.
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*/
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status = RadRWVPattern(RAD_AES_SUBCODE_TXA_LU0,
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RAD_NUMBER_AES_SUBCODE1,
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pattern);
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globStatus |= status;
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status = 0;
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status = RadRWVPattern(RAD_AES_SUBCODE_TXA_RV2,
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RAD_NUMBER_AES_SUBCODE2,
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pattern);
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globStatus |= status;
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status = 0;
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if(verbose) {
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msg_printf(DBG,"RAD AES Subcode Tx A R/W test: ");
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if(status)
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msg_printf(DBG,"FAIL\n");
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else
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msg_printf(DBG,"OK\n");
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}
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status = RadRWVPattern(RAD_AES_SUBCODE_TXB_LU0,
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RAD_NUMBER_AES_SUBCODE1,
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pattern);
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globStatus |= status;
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status = 0;
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status = RadRWVPattern(RAD_AES_SUBCODE_TXB_RV2,
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RAD_NUMBER_AES_SUBCODE2,
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pattern);
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globStatus |= status;
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status = 0;
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if(verbose) {
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msg_printf(DBG,"AES Subcode Tx B Ram R/W test: ");
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if(status)
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msg_printf(DBG,"FAIL\n");
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else
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msg_printf(DBG,"OK\n");
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}
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status = RadRWVPattern(RAD_ADAT_SUBCODE_RXA_U0_0,
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RAD_NUMBER_ADAT_SUBCODE,
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pattern);
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if(verbose) {
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msg_printf(DBG,"RAD ADAT Subcode Rx A Ram R/W test: ");
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if(status)
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msg_printf(DBG,"FAIL\n");
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else
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msg_printf(DBG,"OK\n");
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}
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globStatus |= status;
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status = 0;
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status = RadRWVPattern(RAD_ADAT_SUBCODE_RXB_U0_0,
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RAD_NUMBER_ADAT_SUBCODE,
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pattern);
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if(verbose) {
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msg_printf(DBG,"RAD ADAT Subcode Rx B Ram R/W test: ");
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if(status)
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msg_printf(DBG,"FAIL\n");
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else
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msg_printf(DBG,"OK\n");
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}
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globStatus |= status;
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status = 0;
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/*
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* AES Subcode has a break in the address due to
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* size requirements in the standard.
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*/
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status = RadRWVPattern(RAD_AES_SUBCODE_RXA_LU0,
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RAD_NUMBER_AES_SUBCODE1,
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pattern);
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if(verbose) {
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msg_printf(DBG,"RAD AES Subcode Rx A R/W test: ");
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if(status)
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msg_printf(DBG,"FAIL\n");
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else
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msg_printf(DBG,"OK\n");
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}
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globStatus |= status;
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status = 0;
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status = RadRWVPattern(RAD_AES_SUBCODE_RXB_RV2,
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RAD_NUMBER_AES_SUBCODE2,
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pattern);
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if(verbose) {
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msg_printf(DBG,"RAD AES Subcode Rx A R/W test: ");
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if(status)
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msg_printf(DBG,"FAIL\n");
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else
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msg_printf(DBG,"OK\n");
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}
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globStatus |= status;
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status = 0;
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status = RadRWVPattern(RAD_AES_SUBCODE_RXB_LU0,
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RAD_NUMBER_AES_SUBCODE1,
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pattern);
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globStatus |= status;
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status = 0;
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status = RadRWVPattern(RAD_AES_SUBCODE_RXB_RV2,
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RAD_NUMBER_AES_SUBCODE2,
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pattern);
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globStatus |= status;
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status = 0;
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if(verbose) {
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msg_printf(DBG,"AES Subcode Rx B Ram R/W test: ");
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if(status)
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msg_printf(DBG,"FAIL\n");
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else
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msg_printf(DBG,"OK\n");
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}
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/*
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* Test Data Tx DMA:
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*/
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status = RadRWVPattern(RAD_ADAT_TX_DATA,
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RAD_NUMBER_DATA,
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pattern);
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if(verbose) {
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msg_printf(DBG,"RAD Tx Data Ram R/W test: ");
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if(status)
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msg_printf(DBG,"FAIL\n");
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else
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msg_printf(DBG,"OK\n");
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}
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globStatus |= status;
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status = 0;
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/*
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* Test Rx Data Ram
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*/
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status = RadRWVPattern(RAD_ADAT_RX_DATA,
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RAD_NUMBER_DATA,
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pattern);
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if(verbose) {
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msg_printf(DBG,"RAD Rx Data Ram R/W test: ");
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if(status)
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msg_printf(DBG,"FAIL\n");
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else
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msg_printf(DBG,"OK\n");
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}
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globStatus |= status;
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status = 0;
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/*
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* Get RAD out of RAD test mode
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*/
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msg_printf(DBG,"Set RAD out of RAM test mode\n");
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SETBITS(value,0x1,0,5);
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RAD_WRITE(RAD_MISC_CONTROL,value);
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/*PIO_REG_WR_32(PCI_MEM_BASE+RAD_MISC_CONTROL, mask32, value);*/
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/*
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* Report Exit code
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*/
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#ifdef NOTNOW
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REPORT_PASS_OR_FAIL(globStatus? 1: 0, "RAD RAM", D_FRU_IP30);
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#endif
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REPORT_PASS_OR_FAIL( &CPU_Test_err[CPU_ERR_RAD_0002], (globStatus ? 1 : 0) );
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}
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RadRWVPattern(uint_t baseRegister,
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uint_t numberOfRegisters,
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int basePattern)
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{
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int status=0, i;
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uint_t readback=0;
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uint_t readbackPattern;
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for(i=0; i<numberOfRegisters; i++) RAD_WRITE(baseRegister+i*4,basePattern+i);
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for(i=0; i<numberOfRegisters; i++) {
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readback = RAD_READ(baseRegister+i*4);
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readbackPattern = basePattern + i;
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msg_printf(DBG,"Addr: %x Read Value %x Actual pattern: %x\n",baseRegister+i*4, readback,
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readbackPattern);
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if(readback != readbackPattern && verbose) {
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msg_printf(ERR,"Read Value %x Actual pattern: %x\n",readback,
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readbackPattern);
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status = 1;
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}
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}
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return status;
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}
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