250 lines
6.5 KiB
C
250 lines
6.5 KiB
C
/*********************************************************************
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* *
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* Title : RadStatusTest *
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* Author: Jimmy Acosta *
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* Date : 03.18.96 *
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* *
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*********************************************************************
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* *
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* Description: *
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* *
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* Test Status DMA transfer. RadStatusTest will write a *
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* predetermined pattern to the working registers and later *
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* confirm their values in main memory after status dma *
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* occurred. *
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* *
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* Test Options: *
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* -s <delay> delay based in PCI clock rate values *
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* -v (Print in verbose mode) *
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* rad_stat -s -v *
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* (C) Copyright 1996 by Silicon Graphics, Inc. *
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* All Rights Reserved. *
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*********************************************************************/
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#include "ide_msg.h"
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#include "uif.h"
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#include "pause.h"
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#include <libsc.h>
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#include <libsk.h>
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#include "sys/types.h"
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#include <sgidefs.h>
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#include "sys/sbd.h"
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#include "d_frus.h"
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#include "uif.h"
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#include "d_godzilla.h"
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#include "d_rad.h"
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#include "d_rad_util.h"
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#include "d_prototypes.h"
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static __uint64_t dmabuf[512/2]; /* Storage place for status dma */
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int RadStatusTest(int argc, char** argv)
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{
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int spin=0, verbose=0, temp2;
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int delay = 0, bad_arg;
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volatile uint_t temp;
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int result=0, i;
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volatile uint_t uitmp=0;
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__uint64_t *Tptr;
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int * Tptr2;
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int status=0;
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if (IsOctaneLx())
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return 100;
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RadConfigBase = RAD_PCI_CFG_BASE; /*default*/
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RadMemoryBase = RAD_PCI_DEVIO_BASE; /*default*/
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/*check args*/
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if (argc > 1) {
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if ( !(strcmp(argv[1], "-s0")) || !(strcmp(argv[1], "-s1"))
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|| !(strcmp(argv[1], "-s2")) || !(strcmp(argv[1], "-s3"))
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) {}
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else {
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msg_printf(INFO, "PCI Slot argument required\n");
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msg_printf(INFO, "Usage: rad_dma -s[0..2]\n");
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return 1; /*non fatal fail*/
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}
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}
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/* get the args */
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argc--; argv++;
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while (argc && argv[0][0]=='-' && argv[0][1]!='\0') {
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switch (argv[0][1]) {
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case 's':
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switch (argv[0][2]) {
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case '0':
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RadConfigBase = SHOE_BRIDGE_BASE | 0x020000;
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RadMemoryBase = SHOE_BRIDGE_BASE | 0x200000;
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break;
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case '1':
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RadConfigBase = SHOE_BRIDGE_BASE | 0x021000;
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RadMemoryBase = SHOE_BRIDGE_BASE | 0x400000;
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break;
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case '2':
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RadConfigBase = SHOE_BRIDGE_BASE | 0x022000;
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RadMemoryBase = SHOE_BRIDGE_BASE | 0x600000;
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break;
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case '3':
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RadConfigBase = SHOE_BRIDGE_BASE | 0x023000;
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RadMemoryBase = SHOE_BRIDGE_BASE | 0x700000;
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break;
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default:
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return 1;
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}
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break;
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default:
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bad_arg++; break;
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}
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argc--; argv++;
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}
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msg_printf(INFO, "Testing RAD DMA at CONF Addr 0x%x, MEM Addr 0x%x\n", RadConfigBase, RadMemoryBase);
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/* switched off
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argc--; argv++;
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while (argc && argv[0][0]=='-' && argv[0][1]!='\0') {
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if(argv[0][1] == 's')
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spin = 1;
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else if(argv[0][1] == 'v')
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verbose = 1;
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argc--; argv++;
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}
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*/
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/*Take this out is -v switched on*/
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verbose = 1;
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spin = 0;
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/*
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* Initialize status dma buffer to 0 __psint_t
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*/
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/* inherited makes last byte 0x00 or 0x80*/
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Tptr =(__uint64_t *) (((__uint64_t)dmabuf & ~127) + 128);
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for(i=0; i<64; i++)
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Tptr[i] = 0x0;
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Tptr2 = (int *)Tptr;
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/*flushbus();sr remove*/
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/*
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* Initialize RAD registers
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*/
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msg_printf(DBG,"Initializing RAD \n");
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result = RadSetup();
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if(result == -1) {
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msg_printf(DBG,"Problem setting up RAD, exiting diagnostic.\n");
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return -1;
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}
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/*
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* Write a pattern to the working DMA registers, so that we can cross
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* check them when they are dma'd by status dma.
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*/
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msg_printf(DBG,"Doing PIO to command line registers \n");
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for(i=0; i<16; i++)
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RAD_WRITE(RAD_PCI_LOADR_ADAT_RX+(i*4), 0x55AA0000+i);
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/*
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* Setup status dma, including value for the delay timer and
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* start it.
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*/
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msg_printf(DBG,"Setting up status dma working registers\n");
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status = RadSetupDMA(RAD_STATUS,Tptr2,2,spin);
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if(status == -1) {
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msg_printf(DBG,"Problems setting up status registers, exiting\n");
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return -1;
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}
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uitmp = 0;
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SETBITS(uitmp,0x7FFF,0x4,8); /* bits 17:2 - timer value */
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SETBITS(uitmp,0x1,spin,1); /* bit 1 - retrigger, 1 = enable */
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SETBITS(uitmp,0x1,1,0); /* bit 0 - status DMA, 1 = enable */
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RAD_WRITE(RAD_STATUS_TIMER,uitmp);
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msg_printf(DBG,"Enabling Status DMA\n");
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if(spin) {
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msg_printf(DBG,"Status DMA: Press space bar to stop dma\n");
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pause(0," ",NULL);
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uitmp = RAD_READ(RAD_STATUS_TIMER);
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SETBITS(uitmp,0x1,0,0); /* Bit 0: Stop status dma */
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RAD_WRITE(RAD_STATUS_TIMER,uitmp);
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}
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else {
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/*
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* Wait for a second to make sure that status dma
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* has been finished, more than enough time since the timer
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* was set to ~2ms delay for the transfer.
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*/
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pause(1,NULL,NULL);
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temp = RAD_READ(RAD_STATUS_TIMER);
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i=0;
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while(temp & 0x1 ) {
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pause(1,NULL,NULL);
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temp = RAD_READ(RAD_STATUS_TIMER);
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if(i++ == 5)
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break;
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}
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}
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FlushAllCaches();
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temp = RAD_READ(RAD_PCI_CONTROL_STATUS);
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msg_printf(DBG,"DMA done\n");
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for(i=0;i<32;i++) msg_printf(DBG,"i= 0x%x, Tptr2= 0x%x\n", i, Tptr2[i]);
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for(i=0;i<16;i++) {
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if(Tptr2[i] == (0x55AA0000+i)) {
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if(verbose)
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msg_printf(DBG,"Word %d: OK\n",i);
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}
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else {
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if(verbose) {
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msg_printf(DBG,"Word %d: FAIL\n",i);
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}
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result++;
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}
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}
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if(Tptr2[31] == 0x80000000) {
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if(verbose)
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msg_printf(DBG,"Word 31: OK\n");
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} else {
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if(verbose)
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msg_printf(DBG,"Word 31: FAIL\n");
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result++;
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}
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/*
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msg_printf(INFO,"RAD Status DMA Test: ");
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if(result) {
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msg_printf(INFO,"FAIL\n");
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msg_printf(INFO,"Number of failures: %d \n",result);
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}
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else msg_printf(INFO,"OK\n");
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return result;
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*/
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#ifdef NOTNOW
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REPORT_PASS_OR_FAIL(result, "RAD Status DMA", D_FRU_IP30);
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#endif
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REPORT_PASS_OR_FAIL( &CPU_Test_err[CPU_ERR_RAD_0003], result );
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}
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