398 lines
10 KiB
C
398 lines
10 KiB
C
#ident "include/net/seeq.h: $Revision: 1.13 $"
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/*
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* Copyright 1989 Silicon Graphics, Inc. All rights reserved.
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*
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* Definitions for the SEEQ 8003 chip when interfaced to the HPC1/HPC3.
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*/
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/* maximum & minimum packet sizes */
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#define EHDR_LEN 14
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#define MAX_TPKT (EHDR_LEN+1500) /* max xmit len (seeq adds crc) */
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#define MIN_TPKT 60 /* min xmit len, unchained pkts */
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#define HPC_RSPACE 3 /* 2 byte offset + 1 status */
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#define MAX_RPKT (MAX_TPKT+HPC_RSPACE) /* max receive length */
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/* SEEQ 8003 external register definitions */
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/* receive status register */
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#define SEQ_RS_OLD 0x80 /* old/new status, set on reg read */
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#define SEQ_RS_GOOD 0x20 /* good frame */
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#define SEQ_RS_END 0x10 /* received end of frame */
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#define SEQ_RS_SHORT 0x08 /* received short frame */
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#define SEQ_RS_DRBL 0x04 /* dribble error */
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#define SEQ_RS_CRC 0x02 /* CRC error */
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#define SEQ_RS_OFLOW 0x01 /* overflow error */
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#if IP22 || IP26 || IP28
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#define RCVSTAT_SHIFT 0
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#define HPC_RBO 0x800 /* receive buffer overflow */
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#define HPC_STRCVDMA_MASK 0x400 /* receive channel active mask */
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#define HPC_STRCVDMA 0x200 /* receive dma started */
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#define HPC_RCV_ENDIAN_LITTLE 0x100 /* receive dma is little endian */
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#define SEQ_RS_LATE_RXDC 0x40 /* combine with status_5_0 (all 0's)
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to signify late receive */
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#define SEQ_RS_TIMEOUT 0x40 /* combine with the status_4 (1) to
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signify timeout */
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#define SEQ_RS_STATUS_5_0 0x3f /* mask for the 6 lowest status bits */
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#else
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#define RCVSTAT_SHIFT 8
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#define HPC_STRCVDMA 0x4000 /* receive dma started */
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#endif /* IP22 || IP26 || IP28 */
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/* receive command register */
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#define SEQ_RC_RNONE 0x0 /* disable seeq receive */
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#define SEQ_RC_RSMB 0xc0 /* recv station/broadcast/multicast */
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#define SEQ_RC_RSB 0x80 /* recv station/broadcast */
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#define SEQ_RC_RALL 0x40 /* receive all frames */
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#define SEQ_RC_INTGOOD 0x20 /* interrupt on good frames */
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#define SEQ_RC_INTEND 0x10 /* interrupt on end of frame */
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#define SEQ_RC_INTSHORT 0x08 /* interrupt on short frame */
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#define SEQ_RC_INTDRBL 0x04 /* interrupt on dribble error */
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#define SEQ_RC_INTCRC 0x02 /* interrupt on CRC error */
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#define SEQ_RC_OFLOW 0x01 /* interrupt on overflow error */
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/* xmit status register */
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#if IP22 || IP26 || IP28
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#define HPC_STTRDMA_MASK 0x400 /* xmit channel active mask */
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#define HPC_STTRDMA 0x200 /* xmit dma started */
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#define HPC_TR_ENDIAN_LITTLE 0x100 /* transmit dma is little endian */
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#define SEQ_XS_OLD 0x80 /* old/new status, set on reg read */
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#define SEQ_XS_LATE_COLL 0x10 /* late collision */
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#define SEQ_XS_SUCCESS 0x08 /* xmit success */
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#define SEQ_XS_16TRY 0x04 /* 16 retries */
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#define SEQ_XS_COLL 0x02 /* collision */
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#define SEQ_XS_UFLOW 0x01 /* underflow */
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#else
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#define SEQ_XS_OLD (0x80 << 16) /* old/new status, set on reg read */
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#define HPC_STTRDMA (0x40 << 16) /* xmit dma started */
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#define SEQ_XS_SUCCESS (0x08 << 16) /* xmit success */
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#define SEQ_XS_16TRY (0x04 << 16) /* 16 retries */
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#define SEQ_XS_COLL (0x02 << 16) /* collision */
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#define SEQ_XS_UFLOW (0x01 << 16) /* underflow */
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#endif /* IP22 || IP26 || IP28 */
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/* on new EDLC only */
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#define SEQ_XS_NO_SQE 0x01
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#define SEQ_XS_NO_CARRIER 0x02
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/* xmit command register */
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#define SEQ_XC_REGBANK0 0x00 /* access reg bank 0 incl station addr */
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#define SEQ_XC_REGBANK1 0x20 /* access reg bank 1 incl mcast-lsb */
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#define SEQ_XC_REGBANK2 0x40 /* access reg bank 2 incl mcast-msb & ctl */
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#define SEQ_XC_INTGOOD 0x08 /* interrupt on good xmit */
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#define SEQ_XC_INT16TRY 0x04 /* interrupt on 16 retries */
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#define SEQ_XC_INTCOLL 0x02 /* interrupt on collision */
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#define SEQ_XC_INTUFLOW 0x01 /* interrupt on underflow */
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/* control register */
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#define SEQ_CTL_NOCARR 0x20 /* enable/clear no carrier on xmit flag */
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#define SEQ_CTL_SHORT 0x10 /* enable/disable recv frame < 14 bytes */
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#define SEQ_CTL_MULTI 0x08 /* enable/disable hash multicast */
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#define SEQ_CTL_SQE 0x04 /* enable/clear sqe flag */
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#define SEQ_CTL_ACOLL 0x02 /* enable/clear all coll counter */
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#define SEQ_CTL_XCOLL 0x01 /* enable/clear xmit coll counter */
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/* HPC1/3 ethernet reg definitions */
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/* HPC enet control register */
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#if IP22 || IP26 || IP28
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#define HPC_MODNORM 0x0 /* mode: 0=normal, 1=loopback */
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#define HPC_FIX_INTR 0x8000 /* start timeout counter after */
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#define HPC_FIX_EOP 0x4000 /* rcv_eop_intr/eop_in_chip is set */
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#define HPC_FIX_RXDC 0x2000 /* clear eop status upon rxdc */
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#define HPC_INTERGAP 0x1000 /* enable writing of intergap reg */
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#else
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#define HPC_RBO 0x08 /* receive buffer overflow */
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#define HPC_MODNORM 0x04 /* mode: 0=loopback, 1=normal */
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#endif /* IP22 || IP26 || IP28 */
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#define HPC_INTPEND 0x02 /* interrupt pending, write 1 clears */
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#define HPC_ERST 0x01 /* ethernet channel reset */
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#if IP20
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typedef volatile struct xd {
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#ifdef _MIPSEB
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volatile u_int
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x_eoxp:1,
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:15,
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x_xie:1,
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:2,
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x_xbcnt:13;
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volatile u_int
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x_eox:1,
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:3,
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x_xbufptr:28;
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#else /* _MIPSEL */
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volatile u_int
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x_xbcnt:13,
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:2,
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x_xie:1,
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:15,
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x_eoxp:1;
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volatile u_int
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x_xbufptr:28,
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:3,
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x_eox:1;
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#endif /* _MIPSEL */
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volatile u_int x_nxdesc; /* (physical) struct xd * */
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__uint32_t x_nxpkt;
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#if _MIPS_SIM == _ABI64
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__uint32_t x_pad0;
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struct mbuf *x_mbuf;
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__uint32_t x_pad1[2];
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#else
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struct mbuf *x_mbuf;
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#endif
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} xd_desc;
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typedef volatile struct rd {
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#ifdef _MIPSEB
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volatile u_int
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r_rown:1,
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:18,
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r_rbcnt:13;
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volatile u_int
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r_eor:1,
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:3,
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r_rbufptr:28;
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#else /* _MIPSEL */
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volatile u_int
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r_rbcnt:13,
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:18,
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r_rown:1;
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volatile u_int
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r_rbufptr:28,
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:3,
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r_eor:1;
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#endif /* _MIPSEL */
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volatile u_int r_nrdesc; /* (physical) struct rd * */
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#if _MIPS_SIM == _ABI64
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__uint32_t r_pad0;
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struct mbuf *r_mbuf;
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__uint32_t r_pad1[2];
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#else
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struct mbuf *r_mbuf;
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#endif
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} rd_desc;
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/*
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* HPC enet register mapping
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*/
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typedef struct {
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u_int fill1;
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u_int fill2;
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volatile u_int xcount; /* hpc debug reg */
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volatile u_int cxbp; /* current xmit buffer pointer */
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volatile u_int nxbdp; /* next xmit buffer desc. pointer */
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volatile u_int xbc; /* xmit byte count */
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volatile u_int xpntr; /* hpc debug reg */
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volatile u_int xfifo; /* hpc debug reg */
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volatile u_int cxbdp; /* current xmit buf desc ptr */
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volatile u_int cpfxbdp; /* curr packet 1st xmit buf desc. ptr */
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volatile u_int ppfxbdp; /* prev pckt 1st xmit buf desc ptr */
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volatile u_int intdelay; /* interrupt delay count */
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u_int fill3; /* hpc debug reg (data 31 to 24) */
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volatile u_int trstat; /* xmit status */
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volatile u_int rcvstat; /* receive status */
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volatile u_int ctl; /* intrpt, channel reset, buf oflow */
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u_int fill4;
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volatile u_int rcount; /* hpc debug reg */
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volatile u_int rbc; /* receive byte count */
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volatile u_int crbp; /* current receive buf ptr */
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volatile u_int nrbdp; /* next receive buf desc ptr */
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volatile u_int crbdp; /* current receive buf desc ptr */
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volatile u_int rpntr; /* hpc debug reg */
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volatile u_int rfifo; /* hpc debug reg */
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u_int fill5[40];
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/*
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* seeq external registers
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*/
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struct {
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union {
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volatile u_int eaddr[6];
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volatile u_int mcast_lsb[6];
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struct {
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volatile u_int mcast_msb[2];
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volatile u_int pktgap;
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volatile u_int ctl;
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} seq_write;
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/* read regs */
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struct {
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volatile u_int coll_xmit[2];
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volatile u_int coll_total[2];
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volatile u_int fill6;
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volatile u_int flags;
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} seq_read;
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} sr;
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volatile u_int csr; /* seeq receive com/stat reg */
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volatile u_int csx; /* seeq xmit cmd/stat reg */
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} seq_reg;
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} *EHIO;
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#endif /* IP20 */
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#if IP22 || IP26 || IP28
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#define XID_MASK ((1 << 5) - 1)
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typedef struct xd {
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u_int x_xbufptr;
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#ifdef _MIPSEB
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u_int x_eox:1,
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x_eoxp:1,
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x_xie:1,
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x_xid:5,
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x_ipg:8,
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x_txd:1,
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:1,
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x_xbcnt:14;
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#else /* _MIPSEL */
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u_int x_xbcnt:14,
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:1,
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x_txd:1,
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x_ipg:8,
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x_xid:5,
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x_xie:1,
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x_eoxp:1,
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x_eox:1;
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#endif /* _MIPSEL */
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__uint32_t x_nxdesc; /* (physical) struct xd * */
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#if _MIPS_SIM == _ABI64
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__uint32_t x_pad0;
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struct mbuf *x_mbuf;
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__uint32_t x_pad1[2];
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#else
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struct mbuf *x_mbuf;
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#endif
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} xd_desc;
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typedef struct rd {
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u_int r_rbufptr;
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#ifdef _MIPSEB
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u_int r_eor:1,
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r_eorp:1,
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r_xie:1,
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:14,
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r_rown:1,
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r_rbcnt:14;
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#else /* _MIPSEL */
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u_int r_rbcnt:14,
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r_rown:1,
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:14,
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r_xie:1,
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r_eorp:1,
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r_eor:1;
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#endif /* _MIPSEL */
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__uint32_t r_nrdesc; /* (physical) struct rd * */
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#if _MIPS_SIM == _ABI64
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__uint32_t r_pad0;
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struct mbuf *r_mbuf;
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__uint32_t r_pad1[2];
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#else
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struct mbuf *r_mbuf;
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#endif
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} rd_desc;
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/*
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* HPC enet register mapping
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*/
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typedef struct {
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u_int fill1[20480];
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volatile u_int crbp; /* current receive buf ptr */
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volatile u_int nrbdp; /* next receive buf desc ptr */
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u_int fill2[1022];
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volatile u_int rbc; /* receive byte count */
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volatile u_int rcvstat; /* receive status */
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volatile u_int rgio; /* receive gio fifo ptr */
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volatile u_int rdev; /* receive device fifo ptr */
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u_int fill3;
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volatile u_int ctl; /* intrpt, channel reset, buf oflow */
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volatile u_int dmacfg; /* dma configuration */
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volatile u_int piocfg; /* pio configuration */
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u_int fill4[1016];
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volatile u_int cxbp; /* current xmit buffer ptr */
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volatile u_int nxbdp; /* next xmit buffer desc ptr */
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u_int fill5[1022];
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volatile u_int xbc; /* xmit byte count */
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volatile u_int trstat; /* xmit status */
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volatile u_int xgio; /* xmit gio fifo ptr */
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volatile u_int xdev; /* xmit device fifo ptr */
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u_int fill6[1020];
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volatile u_int crbdp; /* current receive desc ptr */
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u_int fill7[2047];
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/* these 2 are ping pong ptrs and are not in order */
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volatile u_int cpfxbdp; /* current/previous packet 1st xmit */
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volatile u_int ppfxbdp; /* desc ptr */
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u_int fill8[59390];
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/*
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* seeq external registers
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*/
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struct {
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union {
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volatile u_int eaddr[6];
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volatile u_int mcast_lsb[6];
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struct {
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volatile u_int mcast_msb[2];
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volatile u_int pktgap;
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volatile u_int ctl;
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} seq_write;
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/* read regs */
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struct {
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volatile u_int coll_xmit[2];
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volatile u_int coll_total[2];
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volatile u_int fill6;
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volatile u_int flags;
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} seq_read;
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} sr;
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volatile u_int csr; /* seeq receive com/stat reg */
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volatile u_int csx; /* seeq xmit cmd/stat reg */
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} seq_reg;
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} *EHIO;
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#endif /* IP22 || IP26 || IP28 */
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#define seq_csr seq_reg.csr
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#define seq_csx seq_reg.csx
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#define seq_eaddr seq_reg.sr.eaddr
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#define seq_mcast_lsb seq_reg.sr.mcast_lsb
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#define seq_mcast_msb seq_reg.sr.seq_write.mcast_msb
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#define seq_pktgap seq_reg.sr.seq_write.pktgap
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#define seq_ctl seq_reg.sr.seq_write.ctl
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#define seq_coll_xmit seq_reg.sr.seq_read.coll_xmit
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#define seq_coll_total seq_reg.sr.seq_read.coll_total
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#define seq_flags seq_reg.sr.seq_read.flags
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