497 lines
18 KiB
C
497 lines
18 KiB
C
/**************************************************************************
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* *
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* Copyright (C) 1995, Silicon Graphics, Inc. *
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* *
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* These coded instructions, statements, and computer programs contain *
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* unpublished proprietary information of Silicon Graphics, Inc., and *
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* are protected by Federal copyright law. They may not be disclosed *
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* to third parties or copied or duplicated in any form, in whole or *
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* in part, without the prior written consent of Silicon Graphics, Inc. *
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* *
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**************************************************************************/
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#ifndef IP32 /* whole file */
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#ifndef __PCI_BRIDGE_H__
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#define __PCI_BRIDGE_H__
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#ident "$Revision: 1.2 $"
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/*
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* bridge.h - bridge chip header file
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*/
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#include <sys/xtalk/xwidget.h> /* generic widget header */
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/* Start: Random stuff */
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/* Widget part number of bridge */
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#define BRIDGE_WIDGET_PART_NUM 0xc002
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/*
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* I/O page size
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*/
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#if _PAGESZ == 4096
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#define IOPFNSHIFT 12 /* 4K per mapped page */
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#else
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#define IOPFNSHIFT 14 /* 16K per mapped page */
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#endif /* _PAGESZ */
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#define IOPGSIZE (1<<IOPFNSHIFT)
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#define IOPG(x) (x>>IOPFNSHIFT)
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/* End: Random stuff */
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/*
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* Bridge address map
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*/
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/* Bridge internal registers
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*/
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#define BRIDGE_WID_ID WIDGET_ID
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#define BRIDGE_WID_STAT WIDGET_STATUS
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#define BRIDGE_WID_ERR_UPPER WIDGET_ERR_UPPER_ADDR
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#define BRIDGE_WID_ERR_LOWER WIDGET_ERR_LOWER_ADDR
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#define BRIDGE_WID_CONTROL WIDGET_CONTROL
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#define BRIDGE_WID_REQ_TIMEOUT WIDGET_REQ_TIMEOUT
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#define BRIDGE_WID_INT_UPPER WIDGET_INTDEST_UPPER_ADDR
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#define BRIDGE_WID_INT_LOWER WIDGET_INTDEST_LOWER_ADDR
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#define BRIDGE_WID_ERR_CMDWORD WIDGET_ERR_CMD_WORD
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#define BRIDGE_WID_LLP WIDGET_LLP_CFG
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#define BRIDGE_WID_TARG_FLUSH WIDGET_TFLUSH
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#define BRIDGE_WID_AUX_ERR 0x00005C /* Aux Error Command Word */
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#define BRIDGE_WID_RESP_UPPER 0x000064 /* Response Buf Upper Addr */
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#define BRIDGE_WID_RESP_LOWER 0x00006C /* Response Buf Lower Addr */
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#define BRIDGE_WID_TST_PIN_CTRL 0x000074 /* Test pin control */
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#define BRIDGE_DIR_MAP 0x000084 /* Direct Map reg */
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#define BRIDGE_RAM_PERR 0x000094 /* SSRAM Parity Error */
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#define BRIDGE_ARB 0x0000A4 /* Arbitration Priority reg */
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#define BRIDGE_NIC 0x0000B4 /* Number In A Can */
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#define BRIDGE_PCI_BUS_TIMEOUT 0x0000C4 /* Bus Timeout Register */
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#define BRIDGE_PCI_CFG 0x0000CC /* PCI Type 1 Config reg */
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#define BRIDGE_PCI_ERR_UPPER 0x0000D4 /* PCI error Upper Addr */
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#define BRIDGE_PCI_ERR_LOWER 0x0000DC /* PCI error Lower Addr */
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#define BRIDGE_INT_STATUS 0x000104 /* Interrupt Status */
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#define BRIDGE_INT_ENABLE 0x00010C /* Interrupt Enables */
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#define BRIDGE_INT_RST_STAT 0x000114 /* Reset Intr Status */
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#define BRIDGE_INT_MODE 0x00011C /* Interrupt Mode */
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#define BRIDGE_INT_DEVICE 0x000124 /* Interrupt Device */
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#define BRIDGE_INT_HOST_ERR 0x00012C /* Host Error Field */
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#define BRIDGE_INT_ADDR0 0x000134 /* Host Address Reg */
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#define BRIDGE_INT_ADDR_OFF 0x000008 /* Host Addr offset (1..7) */
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#define BRIDGE_INT_ADDR(x) (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF)
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#define BRIDGE_DEVICE0 0x000204 /* Device 0 */
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#define BRIDGE_DEVICE_OFF 0x000008 /* Device offset (1..7) */
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#define BRIDGE_DEVICE(x) (BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF)
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#define BRIDGE_WR_REQ_BUF0 0x000244 /* Write Request Buffer 0 */
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#define BRIDTE_WR_REQ_BUF_OFF 0x000008 /* Buffer Offset (1..7) */
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#define BRIDGE_WR_REQ_BUF(x) (BRIDGE_WR_REQ_BUF0+(x)*BRIDTE_WR_REQ_BUF_OFF)
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#define BRIDGE_EVEN_RESP 0x000284 /* Even Device Response Buf */
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#define BRIDGE_ODD_RESP 0x00028C /* Odd Device Response Buf */
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#define BRIDGE_RESP_STATUS 0x000294 /* Read Response Status reg */
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#define BRIDGE_RESP_CLEAR 0x00029C /* Read Response Clear reg */
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/* Bridge I/O space */
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#define BRIDGE_ATE_RAM 0x00010000 /* Internal Addr Xlat Ram */
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#define BRIDGE_RRB_RAM 0x00018000 /* Read Response Buffer */
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#define BRIDGE_TYPE0_CFG_DEV0 0x00020000 /* Type 0 Cfg, Device 0 */
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#define BRIDGE_TYPE0_CFG_OFF 0x00001000 /* Type 0 Cfg Offset (1..7) */
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#define BRIDGE_TYPE0_CFG_DEV(x) (BRIDGE_TYPE0_CFG_DEV0+(x)*BRIDGE_TYPE0_CFG_OFF)
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#define BRIDGE_PCI_IACK 0x00030000 /* PCI Interrupt Ack */
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#define BRIDGE_EXT_SSRAM 0x00080000 /* Extern SSRAM (ATE) */
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/* Bridge device IO spaces */
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#define BRIDGE_DEV_CNT 8 /* Up to 8 devices per bridge */
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#define BRIDGE_DEVIO0 0x00200000 /* Device IO 0 Addr */
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#define BRIDGE_DEVIO1 0x00400000 /* Device IO 1 Addr */
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#define BRIDGE_DEVIO2 0x00600000 /* Device IO 2 Addr */
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#define BRIDGE_DEVIO_OFF 0x00100000 /* Device IO Offset (3..7) */
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#define BRIDGE_DEVIO_2MB 0x00200000 /* Device IO Offset (0..1) */
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#define BRIDGE_DEVIO_1MB 0x00100000 /* Device IO Offset (2..7) */
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#define BRIDGE_DEVIO(x) ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB)
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#define BRIDGE_EXTERNAL_FLASH 0x00C00000 /* External Flash PROMS */
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/* Bridge RAM sizes */
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#define BRIDGE_ATE_RAM_SIZE 0x00000400 /* 1kB ATE RAM */
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#define BRIDGE_RRB_RAM_SIZE 0x00000800 /* 2kB Read Response Buffer */
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/* the SSRAM size is determined from the control register */
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#define BRIDGE_SSRAM_512K 0x00080000 /* 512kB */
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#define BRIDGE_SSRAM_128K 0x00020000 /* 128kB */
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#define BRIDGE_SSRAM_64K 0x00010000 /* 64kB */
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#define BRIDGE_SSRAM_0K 0x00000000 /* 0kB */
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/* Bridge widget control register bits definition */
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#define BRIDGE_CTRL_FLASH_WR_EN (0x1 << 31)
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#define BRIDGE_CTRL_EN_CLK50 (0x1 << 30)
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#define BRIDGE_CTRL_EN_CLK40 (0x1 << 29)
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#define BRIDGE_CTRL_EN_CLK33 (0x1 << 28)
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#define BRIDGE_CTRL_RST(n) ((n) << 24)
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#define BRIDGE_CTRL_RST_MASK (BRIDGE_CTRL_RST(0xF))
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#define BRIDGE_CTRL_RST_PIN(x) (BRIDGE_CTRL_RST(0x1 << (x)))
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#define BRIDGE_CTRL_IO_SWAP (0x1 << 23)
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#define BRIDGE_CTRL_MEM_SWAP (0x1 << 22)
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#define BRIDGE_CTRL_PAGE_SIZE (0x1 << 21)
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#define BRIDGE_CTRL_SS_PAR_BAD (0x1 << 20)
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#define BRIDGE_CTRL_SS_PAR_EN (0x1 << 19)
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#define BRIDGE_CTRL_SSRAM_SIZE(n) ((n) << 17)
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#define BRIDGE_CTRL_SSRAM_SIZE_MASK (BRIDGE_CTRL_SSRAM_SIZE(0x3))
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#define BRIDGE_CTRL_SSRAM_512K (BRIDGE_CTRL_SSRAM_SIZE(0x3))
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#define BRIDGE_CTRL_SSRAM_128K (BRIDGE_CTRL_SSRAM_SIZE(0x2))
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#define BRIDGE_CTRL_SSRAM_64K (BRIDGE_CTRL_SSRAM_SIZE(0x1))
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#define BRIDGE_CTRL_SSRAM_1K (BRIDGE_CTRL_SSRAM_SIZE(0x0))
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#define BRIDGE_CTRL_F_BAD_PKT (0x1 << 16)
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#define BRIDGE_CTRL_LLP_XBAR_CRD(n) ((n) << 12)
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#define BRIDGE_CTRL_LLP_XBAR_CRD_MASK (BRIDGE_CTRL_LLP_XBAR_CRD(0xf))
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#define BRIDGE_CTRL_CLR_RLLP_CNT (0x1 << 11)
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#define BRIDGE_CTRL_CLR_TLLP_CNT (0x1 << 10)
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#define BRIDGE_CTRL_SYS_END (0x1 << 9)
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#define BRIDGE_CTRL_MAX_TRANS(n) ((n) << 4)
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#define BRIDGE_CTRL_MAX_TRANS_MASK (BRIDGE_CTRL_MAX_TRANS(0x1f))
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#define BRIDGE_CTRL_WIDGET_ID(n) ((n) << 0)
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#define BRIDGE_CTRL_WIDGET_ID_MASK (BRIDGE_CTRL_WIDGET_ID(0xf))
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/* Bridge direct mapping register bits definition */
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#define BRIDGE_DIRMAP_W_ID_SHFT 20
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#define BRIDGE_DIRMAP_W_ID (0xf << BRIDGE_DIRMAP_W_ID_SHFT)
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#define BRIDGE_DIRMAP_RMF_64 (0x1 << 18)
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#define BRIDGE_DIRMAP_ADD512 (0x1 << 17)
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#define BRIDGE_DIRMAP_OFF (0x1ffff << 0)
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/* Bridge interrupt status register bits definition */
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#define BRIDGE_ISR_MULTI_ERR (0x1 << 31)
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#define BRIDGE_ISR_PMU_ESIZE_FAULT (0x1 << 30)
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#define BRIDGE_ISR_UNEXP_RESP (0x1 << 29)
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#define BRIDGE_ISR_BAD_XRESP_PKT (0x1 << 28)
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#define BRIDGE_ISR_BAD_XREQ_PKT (0x1 << 27)
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#define BRIDGE_ISR_RESP_XTLK_ERR (0x1 << 26)
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#define BRIDGE_ISR_REQ_XTLK_ERR (0x1 << 25)
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#define BRIDGE_ISR_INVLD_ADDR (0x1 << 24)
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#define BRIDGE_ISR_UNSUPPORTED_XOP (0x1 << 23)
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#define BRIDGE_ISR_XREQ_FIFO_OFLOW (0x1 << 22)
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#define BRIDGE_ISR_LLP_REC_SNERR (0x1 << 21)
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#define BRIDGE_ISR_LLP_REC_CBERR (0x1 << 20)
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#define BRIDGE_ISR_LLP_RCTY (0x1 << 19)
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#define BRIDGE_ISR_LLP_TX_RETRY (0x1 << 18)
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#define BRIDGE_ISR_LLP_TCTY (0x1 << 17)
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#define BRIDGE_ISR_SSRAM_PERR (0x1 << 16)
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#define BRIDGE_ISR_PCI_ABORT (0x1 << 15)
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#define BRIDGE_ISR_PCI_PARITY (0x1 << 14)
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#define BRIDGE_ISR_PCI_SERR (0x1 << 13)
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#define BRIDGE_ISR_PCI_PERR (0x1 << 12)
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#define BRIDGE_ISR_PCI_MST_TIMEOUT (0x1 << 11)
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#define BRIDGE_ISR_PCI_RETRY_CNT (0x1 << 10)
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#define BRIDGE_ISR_XREAD_REQ_TIMEOUT (0x1 << 9)
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#define BRIDGE_ISR_GIO_B_ENBL_ERR (0x1 << 8)
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#define BRIDGE_ISR_INT_MSK (0xff << 0)
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#define BRIDGE_ISR_INT(x) (0x1 << (x))
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/* Bridge interrupt enable register bits definition */
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#define BRIDGE_IMR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP
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#define BRIDGE_IMR_PMU_ESIZE_FAULT BRIDGE_ISR_PMU_ESIZE_FAULT
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#define BRIDGE_IMR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT
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#define BRIDGE_IMR_BAD_XREQ_PKT BRIDGE_ISR_BAD_XREQ_PKT
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#define BRIDGE_IMR_RESP_XTLK_ERR BRIDGE_ISR_RESP_XTLK_ERR
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#define BRIDGE_IMR_REQ_XTLK_ERR BRIDGE_ISR_REQ_XTLK_ERR
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#define BRIDGE_IMR_INVLD_ADDR BRIDGE_ISR_INVLD_ADDR
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#define BRIDGE_IMR_UNSUPPORTED_XOP BRIDGE_ISR_UNSUPPORTED_XOP
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#define BRIDGE_IMR_XREQ_FIFO_OFLOW BRIDGE_ISR_XREQ_FIFO_OFLOW
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#define BRIDGE_IMR_LLP_REC_SNERR BRIDGE_ISR_LLP_REC_SNERR
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#define BRIDGE_IMR_LLP_REC_CBERR BRIDGE_ISR_LLP_REC_CBERR
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#define BRIDGE_IMR_LLP_RCTY BRIDGE_ISR_LLP_RCTY
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#define BRIDGE_IMR_LLP_TX_RETRY BRIDGE_ISR_LLP_TX_RETRY
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#define BRIDGE_IMR_LLP_TCTY BRIDGE_ISR_LLP_TCTY
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#define BRIDGE_IMR_SSRAM_PERR BRIDGE_ISR_SSRAM_PERR
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#define BRIDGE_IMR_PCI_ABORT BRIDGE_ISR_PCI_ABORT
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#define BRIDGE_IMR_PCI_PARITY BRIDGE_ISR_PCI_PARITY
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#define BRIDGE_IMR_PCI_SERR BRIDGE_ISR_PCI_SERR
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#define BRIDGE_IMR_PCI_PERR BRIDGE_ISR_PCI_PERR
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#define BRIDGE_IMR_PCI_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT
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#define BRIDGE_IMR_PCI_RETRY_CNT BRIDGE_ISR_PCI_RETRY_CNT
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#define BRIDGE_IMR_XREAD_REQ_TIMEOUT BRIDGE_ISR_XREAD_REQ_TIMEOUT
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#define BRIDGE_IMR_GIO_B_ENBL_ERR BRIDGE_ISR_GIO_B_ENBL_ERR
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#define BRIDGE_IMR_INT_MSK BRIDGE_ISR_INT_MSK
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#define BRIDGE_IMR_INT(x) BRIDGE_ISR_INT(x)
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/* Bridge interrupt reset register bits definition */
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#define BRIDGE_IRR_MULTI_CLR (0x1 << 6)
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#define BRIDGE_IRR_CRP_GRP_CLR (0x1 << 5)
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#define BRIDGE_IRR_RESP_BUF_GRP_CLR (0x1 << 4)
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#define BRIDGE_IRR_REQ_DSP_GRP_CLR (0x1 << 3)
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#define BRIDGE_IRR_LLP_GRP_CLR (0x1 << 2)
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#define BRIDGE_IRR_SSRAM_GRP_CLR (0x1 << 1)
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#define BRIDGE_IRR_PCI_GRP_CLR (0x1 << 0)
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#define BRIDGE_IRR_ALL_CLR 0x7f
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#define BRIDGE_IRR_CRP_GRP (BRIDGE_ISR_UNEXP_RESP | \
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BRIDGE_ISR_XREQ_FIFO_OFLOW)
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#define BRIDGE_IRR_RESP_BUF_GRP (BRIDGE_ISR_BAD_XRESP_PKT | \
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BRIDGE_ISR_RESP_XTLK_ERR | \
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BRIDGE_ISR_XREAD_REQ_TIMEOUT)
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#define BRIDGE_IRR_REQ_DSP_GRP (BRIDGE_ISR_UNSUPPORTED_XOP | \
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BRIDGE_ISR_BAD_XREQ_PKT | \
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BRIDGE_ISR_REQ_XTLK_ERR | \
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BRIDGE_ISR_INVLD_ADDR)
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#define BRIDGE_IRR_LLP_GRP (BRIDGE_ISR_LLP_REC_SNERR | \
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BRIDGE_ISR_LLP_REC_CBERR | \
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BRIDGE_ISR_LLP_RCTY | \
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BRIDGE_ISR_LLP_TX_RETRY | \
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BRIDGE_ISR_LLP_TCTY)
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#define BRIDGE_IRR_SSRAM_GRP (BRIDGE_ISR_SSRAM_PERR | \
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BRIDGE_ISR_PMU_ESIZE_FAULT)
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#define BRIDGE_IRR_PCI_GRP (BRIDGE_ISR_PCI_ABORT | \
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BRIDGE_ISR_PCI_PARITY | \
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BRIDGE_ISR_PCI_SERR | \
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BRIDGE_ISR_PCI_PERR | \
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BRIDGE_ISR_PCI_MST_TIMEOUT | \
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BRIDGE_ISR_PCI_RETRY_CNT | \
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BRIDGE_ISR_GIO_B_ENBL_ERR)
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/* Bridge INT_DEV register bits definition */
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#define BRIDGE_INT_DEV_SHFT(n) ((n)*3)
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#define BRIDGE_INT_DEV_MASK(n) (0x7 << BRIDGE_INT_DEV_SHFT(n))
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/* Bridge interrupt(x) register bits definition */
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#define BRIDGE_INT_ADDR_HOST 0x0001FF00
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#define BRIDGE_INT_ADDR_FLD 0x000000FF
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/* Bridge device(x) register bits definition */
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#define BRIDGE_DEV_ERR_LOCK_EN 0x10000000
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#define BRIDGE_DEV_PAGE_CHK_EN 0x08000000
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#define BRIDGE_DEV_FORCE_PCI_PAR 0x04000000
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#define BRIDGE_DEV_VIRTUAL_EN 0x02000000
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#define BRIDGE_DEV_PMU_WRGA_EN 0x01000000
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#define BRIDGE_DEV_DIR_WRGA_EN 0x00800000
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#define BRIDGE_DEV_DEV_SIZE 0x00400000
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#define BRIDGE_DEV_RT 0x00200000
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#define BRIDGE_DEV_SWAP_PMU 0x00100000
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#define BRIDGE_DEV_SWAP_DIR 0x00080000
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#define BRIDGE_DEV_PREF 0x00040000
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#define BRIDGE_DEV_PRECISE 0x00020000
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#define BRIDGE_DEV_COH 0x00010000
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#define BRIDGE_DEV_BARRIER 0x00008000
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#define BRIDGE_DEV_GBR 0x00004000
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#define BRIDGE_DEV_DEV_SWAP 0x00002000
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#define BRIDGE_DEV_DEV_IO_MEM 0x00001000
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#define BRIDGE_DEV_OFF_MASK 0x00000fff
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/* Bridge interrupt mode register bits definition */
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#define BRIDGE_INTMODE_CLR_PKT_EN(x) (0x1 << (x))
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/* this should be written to the xbow's link_control(x) register */
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#define BRIDGE_CREDIT 3
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/* Ranges of PCI bus space that can be accessed via PIO from xtalk */
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#define BRIDGE_MIN_PIO_ADDR_MEM 0x00000000 /* 1G PCI memory space */
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#define BRIDGE_MAX_PIO_ADDR_MEM 0x3fffffff
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#define BRIDGE_MIN_PIO_ADDR_IO 0x00000000 /* 4G PCI IO space */
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#define BRIDGE_MAX_PIO_ADDR_IO 0xffffffff
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#define PCI32_LOCAL_BASE 0
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#define PCI32_MAPPED_BASE 0x40000000
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#define PCI32_DIRECT_BASE 0x80000000
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#define PCI64_BASE 0x100000000
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#if LANGUAGE_C
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#define IS_PCI32_LOCAL(x) ((ulong_t)(x) < PCI32_MAPPED_BASE)
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#define IS_PCI32_MAPPED(x) ((ulong_t)(x) < PCI32_DIRECT_BASE && \
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(ulong_t)(x) >= PCI32_MAPPED_BASE)
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#define IS_PCI32_DIRECT(x) ((ulong_t)(x) >= PCI32_MAPPED_BASE)
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#define IS_PCI64(x) ((ulong_t)(x) >= PCI64_BASE)
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#endif /* LANGUAGE_C */
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/* The GIO address space.
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*/
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#define GIO_LOCAL_BASE 0x00000000
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#define GIO_MAPPED_BASE 0x40000000
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#define GIO_DIRECT_BASE 0x80000000
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#define GIO64_BASE 0x100000000
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#if LANGUAGE_C
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#define IS_GIO_LOCAL(x) ((ulong_t)(x) < GIO_MAPPED_BASE)
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#define IS_GIO_MAPPED(x) ((ulong_t)(x) < GIO_DIRECT_BASE && \
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(ulong_t)(x) >= GIO_MAPPED_BASE)
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#define IS_GIO_DIRECT(x) ((ulong_t)(x) >= GIO_MAPPED_BASE)
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#define IS_GIO64(x) ((ulong_t)(x) >= GIO64_BASE)
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#endif /* LANGUAGE_C */
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/* PCI to xtalk mapping
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*/
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/* given a DIR_OFF value and a pci/gio 32 bits direct address, determine
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* which xtalk address is accessed
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*/
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#define BRIDGE_DIRECT_32_SEG_SIZE 0x80000000
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#define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr) \
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((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE + \
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|
((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE)
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|
|
|
|
|
/* 64-bit address attribute masks */
|
|
#define PCI64_ATTR_TARG 0xf000000000000000
|
|
#define PCI64_ATTR_PREF 0x0800000000000000
|
|
#define PCI64_ATTR_PREC 0x0400000000000000
|
|
#define PCI64_ATTR_VIRTUAL 0x0200000000000000
|
|
#define PCI64_ATTR_BAR 0x0100000000000000
|
|
#define PCI64_ATTR_RMF 0x00ff000000000000
|
|
|
|
#if LANGUAGE_C
|
|
/* Address translation entry for mapped pci32 accesses */
|
|
typedef struct ate_s {
|
|
union {
|
|
__uint64_t rmf:16,
|
|
addr:36,
|
|
targ:4,
|
|
reserved:3,
|
|
barrier:1,
|
|
prefetch:1,
|
|
precise:1,
|
|
coherent:1,
|
|
valid:1;
|
|
int ate_bits[2];
|
|
} x;
|
|
} ate_t;
|
|
#endif /* LANGUAGE_C */
|
|
|
|
#define ATE_V 0x01
|
|
#define ATE_CO 0x02
|
|
#define ATE_PREC 0x04
|
|
#define ATE_PREF 0x08
|
|
#define ATE_BAR 0x10
|
|
#define ATE_SWAP 0x20
|
|
|
|
#define ATE_PFNSHIFT 12
|
|
#define ATE_TIDSHIFT 8
|
|
#define ATE_RMFSHIFT 48
|
|
|
|
/* Create an ATE directed at local memory */
|
|
#define mkate(mode,pfn) \
|
|
(mode | pfn << ATE_PFNSHIFT | TID_MEMORY << ATE_TIDSHIFT)
|
|
|
|
/* Create an ATE directed at tid */
|
|
#define mkate_tid(mode,pfn,tid) \
|
|
(mode | pfn << ATE_PFNSHIFT | tid << ATE_TIDSHIFT)
|
|
|
|
/* Create an ATE directed at tid/rmf */
|
|
#define mkate_rmf(mode,pfn,tid,rmf) \
|
|
(mode | pfn << ATE_PFNSHIFT | rmf << ATE_RMFSHIFT | tid << ATE_TIDSHIFT)
|
|
|
|
#define BRIDGE_INTERNAL_ATES 128
|
|
#define BRIDGE_ATE_VPN_MASK 0x3ffff000
|
|
|
|
#if LANGUAGE_C
|
|
/* XXX does any code use this ? */
|
|
#define ate_dropin(ba,pate) \
|
|
(ba & BRIDGE_ATE_VPN_MASK >> IOPFNSHIFT) >= BRIDGE_INTERNAL_ATES ? \
|
|
atemem[ba & BRIDGE_ATE_VPN_MASK >> IOPFNSHIFT] = *pate : \
|
|
atebridge[ba & BRIDGE_ATE_VPN_MASK >> IOPFNSHIFT] = *pate
|
|
|
|
/* Bridge chip registers are 32 bits wide. 32-bits access only */
|
|
|
|
typedef __uint32_t bridgereg_t;
|
|
|
|
/* Bridge chip registers */
|
|
typedef volatile struct bridge_s {
|
|
widget_cfg_t b_widget; /* 0x000 */
|
|
|
|
bridgereg_t b_pad_0;
|
|
bridgereg_t b_aux_err_cmd_word; /* 0x05c */
|
|
bridgereg_t b_pad_1;
|
|
bridgereg_t b_resp_buf_upp_addr; /* 0x064 */
|
|
bridgereg_t b_pad_2;
|
|
bridgereg_t b_resp_buf_low_addr; /* 0x06c */
|
|
bridgereg_t b_pad_3[5];
|
|
bridgereg_t b_dir_map; /* 0x084 */
|
|
bridgereg_t b_pad_4[3];
|
|
bridgereg_t b_ssram_perr; /* 0x094 */
|
|
bridgereg_t b_pad_5[3];
|
|
bridgereg_t b_arb_pri; /* 0x0a4 */
|
|
bridgereg_t b_pad_6[3];
|
|
bridgereg_t b_nic; /* 0x0b4 */
|
|
bridgereg_t b_pad_7[3];
|
|
bridgereg_t b_pci_timeout; /* 0x0c4 */
|
|
bridgereg_t b_pad_8;
|
|
bridgereg_t b_pci_type1_cfg; /* 0x0cc */
|
|
bridgereg_t b_pad_9;
|
|
bridgereg_t b_pci_err_upp_addr; /* 0x0d4 */
|
|
bridgereg_t b_pad_10;
|
|
bridgereg_t b_pci_err_low_addr; /* 0x0dc */
|
|
bridgereg_t b_pad_11[9];
|
|
bridgereg_t b_int_status; /* 0x104 */
|
|
bridgereg_t b_pad_12;
|
|
bridgereg_t b_int_enable; /* 0x10c */
|
|
bridgereg_t b_pad_13;
|
|
bridgereg_t b_reset_int_status; /* 0x114 */
|
|
bridgereg_t b_pad_14;
|
|
bridgereg_t b_int_mode; /* 0x11c */
|
|
bridgereg_t b_pad_15;
|
|
bridgereg_t b_int_dev; /* 0x124 */
|
|
bridgereg_t b_pad_16;
|
|
bridgereg_t b_host_err_field; /* 0x12c */
|
|
|
|
struct { /* 0x130 */
|
|
bridgereg_t b_pad_17;
|
|
bridgereg_t addr;
|
|
} b_int_host[8];
|
|
|
|
bridgereg_t b_pad_18[36];
|
|
|
|
struct { /* 0x200 */
|
|
bridgereg_t b_pad_19;
|
|
bridgereg_t reg;
|
|
} b_dev[8];
|
|
|
|
struct { /* 0x240 */
|
|
bridgereg_t b_pad_20;
|
|
bridgereg_t reg;
|
|
} b_wr_req_buf[8];
|
|
|
|
bridgereg_t b_pad_21;
|
|
bridgereg_t b_even_dev_resp_buf; /* 0x284 */
|
|
bridgereg_t b_pad_22;
|
|
bridgereg_t b_odd_dev_resp_buf; /* 0x28c */
|
|
bridgereg_t b_pad_23;
|
|
bridgereg_t b_rd_resp_buf_status; /* 0x294 */
|
|
bridgereg_t b_pad_24;
|
|
bridgereg_t b_rd_resp_buf_clear; /* 0x29c */
|
|
|
|
char b_pad_25[BRIDGE_EXT_SSRAM-0x2A0];
|
|
|
|
__uint64_t b_ext_ssram[256<<10]; /* 0x80000 */
|
|
|
|
} bridge_t;
|
|
|
|
#define BRIDGE_K1PTR ((bridge_t *)PHYS_TO_COMPATK1(BRIDGE_BASE))
|
|
|
|
#define BRIDGE_CLR_INT(b,d) (((volatile bridge_t *)b)->b_clr_int = 1 << (d))
|
|
|
|
typedef struct bridge_dev_cfg_s {
|
|
uint devicecfg; /* values for device(x) register */
|
|
char intr; /* which interrupt (0-7) */
|
|
char intmode; /* interrupt modes */
|
|
uint hostaddr; /* values for interrupt(x) host register */
|
|
uint pcivec; /* pci vector used by this device */
|
|
} bridge_dev_cfg_t;
|
|
|
|
extern void init_bridge(bridge_t *);
|
|
|
|
#endif /* LANGUAGE_C */
|
|
|
|
#endif /* __PCI_BRIDGE_H__ */
|
|
#endif /*ndef IP32 */
|