279 lines
12 KiB
C
279 lines
12 KiB
C
/**************************************************************************
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* *
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* Copyright (C) 1992, Silicon Graphics, Inc. *
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* *
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* These coded instructions, statements, and computer programs contain *
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* unpublished proprietary information of Silicon Graphics, Inc., and *
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* are protected by Federal copyright law. They may not be disclosed *
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* to third parties or copied or duplicated in any form, in whole or *
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* in part, without the prior written consent of Silicon Graphics, Inc. *
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* *
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**************************************************************************/
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/*
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* wd95a.h -- Western Digital 95a chip and associated data structures.
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*/
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#ident "$Revision: 1.1 $"
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#ifndef _SYS_WD95A_
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#define _SYS_WD95A_
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/*
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* register definitions - Setup Mode
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*/
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#define WD95A_S_CTL 0 /* control register */
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#define WD95A_S_SCNF 2 /* scsi configuration */
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#define WD95A_S_OWNID 4 /* Own ID register */
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#define WD95A_S_TIMOUT 6 /* Sel & Resel timout period */
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#define WD95A_S_SLEEP 8 /* Sleep Countdown register */
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#define WD95A_S_TIMER 10 /* scsi timeout countdown residue */
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#define WD95A_S_CDBSIZ1 12 /* Special CDB Size reg (grp 3,4) */
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#define WD95A_S_CDBSIZ2 14 /* Special CDB Size reg (grp 6,7) */
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#define WD95A_S_IDFLAG0 16 /* SCSI-ID specific flags (0..7) */
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#define WD95A_S_IDFLAG1 18 /* SCSI-ID specific flags (8..15) */
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#define WD95A_S_DMACNF 20 /* DMA Configuration */
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#define WD95A_S_DMATIM 22 /* DMA Timing control */
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#define WD95A_S_TEST0 24 /* Factory Test Register */
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#define WD95A_S_SC0 26 /* SCSI Low-level control */
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#define WD95A_S_SC1 28 /* SCSI Low-level control */
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#define WD95A_S_SC2 30 /* SCSI Low-level control */
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#define WD95A_S_SC3 32 /* SCSI Low-level control */
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#define WD95A_S_CSADR 34 /* WCS Address Register */
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#define WD95A_S_CSPRT0 36 /* WCS port for window 0 */
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#define WD95A_S_CSPRT1 38 /* WCS port for window 1 */
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#define WD95A_S_CSPRT2 40 /* WCS port for window 2 */
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#define WD95A_S_CSPRT3 42 /* WCS port for window 3 */
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#define WD95A_S_SQSEL 44 /* WCS Sel reponse addr */
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#define WD95A_S_SQRSL 46 /* WCS ReSel reponse addr */
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#define WD95A_S_SQDMA 48 /* WCS Start addr for DMA req */
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#define WD95A_S_DPRADD 50 /* DPR address Pointer */
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#define WD95A_S_DPRTC 52 /* DPR Transfer Counter */
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#define WD95A_S_PLR 54 /* Physical:Logical Block Ratio */
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#define WD95A_S_PSIZE0 56 /* Physical Block Size */
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#define WD95A_S_PSIZE1 58 /* Physical Block Size */
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#define WD95A_S_PING 60 /* Mirroring Ping-pong value */
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#define WD95A_S_CMPIX 62 /* Data Compare Index */
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#define WD95A_S_CMPVAL 64 /* Data Compare Value Register */
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#define WD95A_S_CMPMASK 66 /* Data Compare Mask Register */
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#define WD95A_S_BBDL 68 /* Buffered BD[0..7] */
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#define WD95A_S_BBDH 70 /* Buffered BD[8..15] */
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#define WD95A_S_CVER 72 /* Chip/Design Version */
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#define WD95A_S_TEST1 74 /* Factory Test Register */
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#define WD95A_S_OFFSET 76 /* REQ/ACK offset counter */
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/*
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* register definitions - Normal Mode
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*/
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#define WD95A_N_CTL 0 /* Control Register */
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#define WD95A_N_CTLA 2 /* Control Register, Auxiliary */
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#define WD95A_N_ISR 4 /* Interrupt Status Register */
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#define WD95A_N_STOPU 6 /* Unexpected Stop Status Register */
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#define WD95A_N_UEI 8 /* Unexpected Event Intr Register */
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#define WD95A_N_ISRM 10 /* ISR Mask Register */
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#define WD95A_N_STOPUM 12 /* STOPU Mask Register */
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#define WD95A_N_UEIM 14 /* UEI Mask Register */
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#define WD95A_N_RESPONSE 16 /* Automatic Response Control */
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#define WD95A_N_SQINT 18 /* WCS Sequencer Interrupt Addr */
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#define WD95A_N_SQADR 20 /* Current addr WCS is executing */
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#define WD95A_N_STC 22 /* SCSI Transfer Control Register */
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#define WD95A_N_SPW 24 /* SCSI Pulse Width Control Reg */
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#define WD95A_N_DESTID 26 /* Destination ID Register */
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#define WD95A_N_SRCID 28 /* Source ID Register */
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#define WD95A_N_FLAG 30 /* Flag Register */
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#define WD95A_N_TC_0_7 32 /* Transfer Count 0..7 */
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#define WD95A_N_TC_8_15 34 /* Transfer Count 8..15 */
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#define WD95A_N_TC_16_23 36 /* Transfer Count 16..23 */
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#define WD95A_N_DATA 38 /* Data Access Port */
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#define WD95A_N_SR 40 /* Status Register */
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#define WD95A_N_FIFOS 42 /* Fifo Status Register */
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#define WD95A_N_PBR 44 /* Physical Block Residue */
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#define WD95A_N_BR0 46 /* Byte Residue */
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#define WD95A_N_BR1 48 /* Byte Residue */
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#define WD95A_N_PINGR 50 /* PING Residue */
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#define WD95A_N_LRCR0 52 /* LRC Residue Register (Low) */
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#define WD95A_N_LRCR1 54 /* LRC Residue Register (High) */
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#define WD95A_N_ODDR 56 /* Odd-Byte Reconnect Register */
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#define WD95A_N_DPR 64 /* address of first DPR */
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#define W95_DPR_R(_reg) (64 + (_reg << 1))
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/* Control register definition */
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#define W95_CTL_SETUP (1 << 0) /* change between setup and normal */
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#define W95_CTL_ABORT (1 << 1) /* Abort any operation */
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#define W95_CTL_KILL (1 << 2) /* Kill any operation */
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#define W95_CTL_LDTC (1 << 3) /* load transfer count */
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#define W95_CTL_LDTCL (1 << 4) /* load transfer count last */
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#define W95_CTL_RSTO (1 << 5) /* reset the scsi bus */
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/* SCNF - SCSI Configuration Register */
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#define W95_SCNF_LRCCE (1 << 0) /* LRC Checking Enable */
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#define W95_SCNF_SCSIL (1 << 1) /* start low-level micro bus control */
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#define W95_SCNF_SPDEN (1 << 2) /* Enable Checking for parity on bus */
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#define W95_SCNF_SPUE (1 << 3) /* SCSI Pullup Enable */
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#define W95_SCNF_RSTFM (1 << 4) /* RSTF output Mask */
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#define W95_SCNF_SCLK (7 << 5) /* LRC Checking Enable */
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#define W95_SCNF_CLK_SHFT 5 /* number of bits to shift a value */
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/* DMACNF - DMA Config register */
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#define W95_DCNF_BURST (1 << 0) /* burst/single cycle DMA */
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#define W95_DCNF_MASTER (1 << 1) /* Master/slave DMA */
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#define W95_DCNF_PGEN (1 << 2) /* Generate Parity */
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#define W95_DCNF_DPEN (1 << 3) /* check for odd parity on dma data */
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#define W95_DCNF_DRQAH (1 << 4) /* Active high for DRQ Signal */
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#define W95_DCNF_DACAH (1 << 5) /* Active high for DACK Signal */
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#define W95_DCNF_DMA16 (1 << 6) /* Transfer size 8/16 */
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#define W95_DCNF_SWAP (1 << 7) /* Swap high and low bytes on dma */
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/* DMATIM - dma timing register */
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#define W95_DTIM_DCLKH (7 << 0) /* DMA read/write high pulse width */
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#define W95_DTIM_DCLKL (7 << 3) /* DMA read/write low pulse width */
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#define W95_DTIM_DSRW (1 << 6) /* DACK setup time from leading edge */
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#define W95_DTIM_DMAOE (1 << 7) /* DMA output enable */
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#define W95_DTIM_CH_SHFT 0 /* bits to shift width value (high) */
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#define W95_DTIM_CL_SHFT 3 /* bits to shift width value (low) */
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/* SC0, SC1 - low level control regiseters */
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#define W95_SC0_SELO (1 << 0) /* SEL output value */
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#define W95_SC0_SELI (1 << 1) /* SEL input value */
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#define W95_SC0_BSYO (1 << 2) /* BSY output value */
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#define W95_SC0_BSYI (1 << 3) /* BSY input value */
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#define W95_SC0_RSTI (1 << 5) /* RST input value */
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#define W95_SC0_SDP (1 << 6) /* SCSI parity for SD 0..7 */
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#define W95_SC0_SDP1 (1 << 7) /* SCSI parity for SD 8..15 */
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#define W95_SC1_REQ (1 << 0) /* REQ output/input value on bus */
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#define W95_SC1_ACK (1 << 1) /* ACK output/input value on bus */
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#define W95_SC1_MSG (1 << 2) /* MSG output/input value on bus */
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#define W95_SC1_CD (1 << 3) /* C/D output/input value on bus */
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#define W95_SC1_IO (1 << 4) /* I/O output/input value on bus */
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#define W95_SC1_ATNL (1 << 5) /* ATN output/input value on bus */
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#define W95_SC1_TGS (1 << 6) /* Target group sel (REQ,MSG,CD,IO) */
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#define W95_SC1_IGS (1 << 7) /* Init. group sel (REQ,MSG,CD,IO) */
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/* CVER - version and bus type reg */
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#define W95_CVER_CVER (0xf)
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#define W95_CVER_CV(_val) ((_val) & W95_CVER_CVER)
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#define W95_CVER_DSENS (1 << 4) /* Differential without SE drive */
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#define W95_CVER_SE (1 << 5) /* Single ended bus */
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/* CTLA - Control Register, Auxiliary */
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#define W95_CTLA_MRM (1 << 0) /* Mirror-Restore Mode */
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#define W95_CTLA_ATNHD (1 << 1) /* Halt data transfer on ATN */
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#define W95_CTLA_LRCGS (1 << 2) /* LRC generation/strip */
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#define W95_CTLA_PIO (1 << 3) /* Polled IO of Fifo enabled */
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#define W95_CTLA_PPEN (1 << 4) /* Ping/pong striping enable */
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#define W95_CTLA_PAS (1 << 5) /* DMA port A enable */
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#define W95_CTLA_PBS (1 << 6) /* DMA port B enable */
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#define W95_CTLA_BYTEC (1 << 7) /* TC pipeline values are byte/block */
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/* ISR - Interrupt status register */
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#define W95_ISR_STOPWCS (1 << 0) /* WCS executed STOP instruction */
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#define W95_ISR_INTWCS (1 << 1) /* WCS instruction with INT set */
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#define W95_ISR_STOPU (1 << 2) /* WCS stopped unexpectedly */
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#define W95_ISR_UEI (1 << 3) /* Unexpected Exception inter */
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#define W95_ISR_BUSYI (1 << 4) /* TC trans from busy to empty */
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#define W95_ISR_VBUSYI (1 << 5) /* TC trans from very busy to busy */
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#define W95_ISR_SREJ (1 << 6) /* micro wrote to SQADR while inhib. */
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#define W95_ISR_INT0 (1 << 7) /* INT output line asserted by ESBC */
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/* STOPU - Unexpected stop status register */
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#define W95_STPU_ABORTI (1 << 0) /* Abort Issued by micro */
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#define W95_STPU_SCSIT (1 << 1) /* SCSI timeout during sel or resel */
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#define W95_STPU_PARE (1 << 2) /* Parity Error */
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#define W95_STPU_LRCE (1 << 3) /* LRC Error */
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#define W95_STPU_TCUND (1 << 4) /* Transfer-count pipeline underrun */
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#define W95_STPU_SOE (1 << 5) /* SCSI offset error */
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/* UEI - Unexpected interrupt status register */
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#define W95_UEI_FIFOE (1 << 0) /* FIFO overflow/underflow */
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#define W95_UEI_ATNI (1 << 1) /* ATN asserted */
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#define W95_UEI_UDISC (1 << 2) /* Unexpected SCSI bus disconnect */
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#define W95_UEI_TCOVR (1 << 3) /* TC pipeline Overrun */
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#define W95_UEI_USEL (1 << 4) /* Unexpected Selection */
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#define W95_UEI_URSEL (1 << 5) /* Unexpected Reselection */
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#define W95_UEI_UPHAS (1 << 6) /* Unexpected SCSI phase */
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#define W95_UEI_RSTINTL (1 << 7) /* Reset received on SCSI bus */
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/* ISRM - Interrupt mask register */
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#define W95_ISRM_STOPWCSM (1 << 0) /* WCS executed Stop instruction */
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#define W95_ISRM_INTWCSM (1 << 1) /* WCS instruction with INT */
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#define W95_ISRM_STOPUM (1 << 2) /* WCS stopped unexpectedly */
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#define W95_ISRM_UEIM (1 << 3) /* Unexpected Exception intr. */
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#define W95_ISRM_BUSYIM (1 << 4) /* TC pipeline becomes empty */
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#define W95_ISRM_VBUSYIM (1 << 5) /* TC pipeline becomes not full */
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#define W95_ISRM_SREJM (1 << 6) /* write to SQADR while inhibited */
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/* STOPUM - Unexpected stop mask register */
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#define W95_STPUM_ABORTM (1 << 0) /* Abort Issued by micro */
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#define W95_STPUM_SCSITM (1 << 1) /* SCSI timeout during sel or resel */
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#define W95_STPUM_PAREM (1 << 2) /* Parity Error */
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#define W95_STPUM_LRCEM (1 << 3) /* LRC Error */
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#define W95_STPUM_TCUNDM (1 << 4) /* Transfer-count pipeline underrun */
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#define W95_STPUM_SOEM (1 << 5) /* SCSI offset error */
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/* UEIM - Unexpected interrupt mask register */
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#define W95_UEIM_FIFOEM (1 << 0) /* FIFO overflow/underflow */
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#define W95_UEIM_ATNIM (1 << 1) /* ATN asserted */
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#define W95_UEIM_UDISCM (1 << 2) /* Unexpected SCSI bus disconnect */
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#define W95_UEIM_TCOVRM (1 << 3) /* TC pipeline Overrun */
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#define W95_UEIM_USELM (1 << 4) /* Unexpected Selection */
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#define W95_UEIM_URSELM (1 << 5) /* Unexpected Reselection */
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#define W95_UEIM_UPHASM (1 << 6) /* Unexpected SCSI phase */
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#define W95_UEIM_RSTINTM (1 << 7) /* Reset received on SCSI bus */
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/* RESPONSE - Automatic response control register */
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#define W95_RESP_SELL (1 << 0) /* Enable low-level sel resp */
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#define W95_RESP_SELH (1 << 1) /* Enable high-level sel resp */
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#define W95_RESP_RSELL (1 << 2) /* Enable low-level resel resp */
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#define W95_RESP_RSELH (1 << 3) /* Enable high-level resel resp */
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#define W95_RESP_AUTOR (1 << 4) /* Automatic reconnect on DMA req */
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#define W95_RESP_AUTOD (1 << 5) /* pause data trans at logical blk */
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#define W95_RESP_ALLRR (1 << 6) /* Auto low-level response reset */
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/* STC - SCSI trasfer control register */
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#define W95_STC_OFF_M 0x3f /* synchronous transfer offset */
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#define W95_STC_WSCSI (1 << 7) /* enable wide SCSI trans for data */
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/* SPW - SCSI Synchronous clock Pulse width */
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#define W95_SPW_SCLKA (7 << 0) /* clock assertion pulse width */
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#define W95_SPW_SCLKA_SFT 0 /* bit position for shift */
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#define W95_SPW_SCLKN (7 << 4) /* clock negation pulse width */
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#define W95_SPW_SCLKN_SFT 4 /* bit position for shift */
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/* SRCID - source ID register */
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#define W95_SRCID_M 0xf /* mask for source id */
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#define W95_SRCID_SIV (1 << 4) /* valid se/reselection */
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/* SR - status register */
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#define W95_SR_BUSY (1 << 0) /* ESBC is busy */
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#define W95_SR_VBUSY (1 << 1) /* ESBC is very busy */
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#define W95_SR_ACTIVE (1 << 2) /* WCS is running */
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#define WCS_NOWHERE 0x7f /* don't do anything */
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#endif /* _SYS_WD95A_ */
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