calmsacibis995
158 lines
4.1 KiB
ArmAsm
158 lines
4.1 KiB
ArmAsm
/**************************************************************************
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* *
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* Copyright (C) 1989-1995, Silicon Graphics, Inc. *
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* *
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* These coded instructions, statements, and computer programs contain *
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* unpublished proprietary information of Silicon Graphics, Inc., and *
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* are protected by Federal copyright law. They may not be disclosed *
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* to third parties or copied or duplicated in any form, in whole or *
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* in part, without the prior written consent of Silicon Graphics, Inc. *
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* *
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**************************************************************************/
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#ident "$Revision: 1.11 $"
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#include "ml/ml.h"
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#if R4000 || R10000
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/* ECC error vector
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*
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* R10000_SPECULATION_WAR: $sp not valid here and running uncached.
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*/
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LEAF(_ecc_errorvec)
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AUTO_CACHE_BARRIERS_DISABLE
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.set noreorder
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NOP_0_4
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#if IP28
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j ECC_SPRING_BOARD # low memory code to handle err
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nop # BDSLOT
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#elif IP30
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/*
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* On entry, we have no registers to play with. We start
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* by saving k1 in cp0 watchli/lo and ll registers. we don't
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* use cp0 context register since four of its bits are hardwired
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* to 0 and in case we come here via the 32-bits tlb miss exception
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* handler, the value in the register may be important
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*/
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.set noat
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MTC0(k1,C0_LLADDR) # save the 32 LSBs of k1
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dsrl32 k1,0
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dsll k1,3 # make sure the 3 LSBs are 0's
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MTC0(k1,C0_WATCHLO) # save the middle 29 bits of k1
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dsrl32 k1,0
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MTC0(k1,C0_WATCHHI) # save the 3 MSBs of k1
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/* determine where the ECC stack located */
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CLI k1,PHYS_TO_COMPATK1(HEART_PRID)
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ld k1,0(k1) # processor id
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dsll k1,3 # *8 to get offset
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PTR_L k1,CACHE_ERR_FRAMEPTR(k1) # ECC handler stack
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sreg k0,EF_K0(k1) # save k0
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sreg AT,EF_AT(k1) # save AT
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/*
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* can't just 'j ecc_exception' since the code crosses the
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* the 256MB segment boundary
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*/
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LA k0,ecc_exception
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LI AT,TO_PHYS_MASK
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and k0,AT
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LI AT,K1BASE
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or k0,AT
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j k0
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nop
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.set at
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#else
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#if defined (SN0)
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/*
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* On SN0, we are in the uncached ualias space. Any relative
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* branches will not work correctly, so for now switch to
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* uncached space.
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*/
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sreg k0, (CACHE_ERR_EFRAME + (EF_K0))(zero)
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sreg k1, (CACHE_ERR_EFRAME + (EF_K1))(zero)
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sreg AT, (CACHE_ERR_EFRAME + (EF_AT))(zero)
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LA k0, 2f
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and k0, ~COMPAT_K1BASE
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PTR_L k1,CACHE_ERR_IBASE_PTR
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bne k1, zero, 1f
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nop
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/*
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* If we take the cache error exception so early that the ibase pointer
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* is not setup, we assume the kernel is replicated on all nodes
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* and jump to our local copy. If this becomes an issue, we should
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* lookup the tlb entry to figure out where the kernel copy resides.
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*/
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LI k1, UALIAS_BASE
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1:
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or k0, k1
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jr k0
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nop
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2:
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#endif /* SN0 */
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j ecc_exception
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nop # BDSLOT
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#endif
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.set reorder
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EXPORT(_ecc_end)
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AUTO_CACHE_BARRIERS_ENABLE
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END(_ecc_errorvec)
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#if (R4000 && R10000)
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EXPORT(_r10k_ecc_errorvec)
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.set noreorder
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NOP_0_4
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j r10k_ecc_exception
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nop # BDSLOT
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.set reorder
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EXPORT(_r10k_ecc_end)
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#endif /* (R4000 && R10000) */
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#endif /* R4000 || R10000 */
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#if defined (SN)
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LEAF(cache_error_exception_vec)
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AUTO_CACHE_BARRIERS_DISABLE
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.set noreorder
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NOP_0_4
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sreg k0, (CACHE_ERR_EFRAME + (EF_K0))(zero)
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sreg k1, (CACHE_ERR_EFRAME + (EF_K1))(zero)
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sreg AT, (CACHE_ERR_EFRAME + (EF_AT))(zero)
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LA k0, 2f
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and k0, ~COMPAT_K1BASE
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PTR_L k1,CACHE_ERR_IBASE_PTR
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bne k1, zero, 1f
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nop
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/*
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* If we take the cache error exception so early that the ibase pointer
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* is not setup, we assume the kernel is replicated on all nodes
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* and jump to our local copy. If this becomes an issue, we should
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* lookup the tlb entry to figure out where the kernel copy resides.
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*/
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LI k1, UALIAS_BASE
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1:
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or k0, k1
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jr k0
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nop
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2:
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j cache_error_exception
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nop # BDSLOT
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.set reorder
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EXPORT(cache_error_exception_vec_end)
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AUTO_CACHE_BARRIERS_ENABLE
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END(cache_error_exception_vec)
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#endif /* SN */
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