133 lines
3.5 KiB
C
133 lines
3.5 KiB
C
/**************************************************************************
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* *
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* Copyright (C) 1994 Silicon Graphics, Inc. *
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* *
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* These coded instructions, statements, and computer programs contain *
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* unpublished proprietary information of Silicon Graphics, Inc., and *
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* are protected by Federal copyright law. They may not be disclosed *
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* to third parties or copied or duplicated in any form, in whole or *
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* in part, without the prior written consent of Silicon Graphics, Inc. *
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* *
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**************************************************************************/
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#ident "$Revision: 1.12 $"
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#ifndef _CACHE_H_
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#define _CACHE_H_
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#if _LANGUAGE_C
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/*
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* Structure to hold the registers at the time of cache test failure.
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* NOTE : This structure should always be kept in sync with STE_OFFSETs
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* defined below.
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*/
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typedef struct {
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__uint64_t
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t0,
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t1,
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t2,
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t3,
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a0,
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a1,
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a2,
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a3,
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v0,
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v1;
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} cache_test_eframe_t;
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/*
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* Define: cache_test_eframe_print
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* Purpose: Print the registers saved after the cache test failure
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* Parameters: cache test eframe
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*/
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#define cache_test_eframe_print(ct_frame) \
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printf("Cache Test Register State:\n" \
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"t0 = %y t1 = %y\n" \
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"t2 = %y t3 = %y\n" \
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"a0 = %y a1 = %y\n" \
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"a2 = %y a3 = %y\n" \
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"v0 = %y v1 = %y\n", \
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ct_frame.t0,ct_frame.t1, \
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ct_frame.t2,ct_frame.t3, \
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ct_frame.a0,ct_frame.a1, \
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ct_frame.a2,ct_frame.a3, \
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ct_frame.v0,ct_frame.v1);
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int cache_size_s(void);
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int cache_size_i(void);
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int cache_size_d(void);
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int cache_test_i(void); /* 0 for success, non-zero for failure */
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int cache_test_d(void);
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int cache_test_s(cache_test_eframe_t *);
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void cache_inval_i(void);
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void cache_inval_d(void);
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void cache_inval_s(void);
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void cache_flush(void);
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void cache_unflush(ulong vaddr, ulong size);
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void cache_dirty(ulong vaddr, ulong paddr, ulong size);
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ulong cache_get_i(ulong vaddr, void *data);
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ulong cache_get_d(ulong vaddr, void *data);
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void cache_get_s(ulong vaddr, void *tags, void *duptags, void *data);
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ulong cache_tag_ecc(ulong tag_value);
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void exec_sscache_asm(ulong base, ulong taglo, ulong taghi);
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void exec_sstag_asm(ulong base, ulong taglo, ulong taghi, ulong way);
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#if 0
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void *cache_copy_pic(void *code, ulong len, ulong vaddr, ulong paddr);
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#endif
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#endif /* _LANGUAGE_C */
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#if _LANGUAGE_ASSEMBLY
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/*
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* NOTE : Maintain these offsets and the above cache_test_eframe structure
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* in sync.
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*/
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#define CTE_OFFSET_t0 0
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#define CTE_OFFSET_t1 CTE_OFFSET_t0 + 8
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#define CTE_OFFSET_t2 CTE_OFFSET_t1 + 8
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#define CTE_OFFSET_t3 CTE_OFFSET_t2 + 8
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#define CTE_OFFSET_a0 CTE_OFFSET_t3 + 8
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#define CTE_OFFSET_a1 CTE_OFFSET_a0 + 8
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#define CTE_OFFSET_a2 CTE_OFFSET_a1 + 8
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#define CTE_OFFSET_a3 CTE_OFFSET_a2 + 8
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#define CTE_OFFSET_v0 CTE_OFFSET_a3 + 8
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#define CTE_OFFSET_v1 CTE_OFFSET_v0 + 8
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/*
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* Define: SCACHE_TEST_GPR_SAVE
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* Purpose: Save the general purpose regiCTEr state when the scache test
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* failed. Useful for additional debugging.
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* Parameters: None
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* Notes: Donot use any registers
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*/
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#define CACHE_TEST_GPR_SAVE \
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sd t0,CTE_OFFSET_t0(a5); \
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sd t1,CTE_OFFSET_t1(a5); \
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sd t2,CTE_OFFSET_t2(a5); \
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sd t3,CTE_OFFSET_t3(a5); \
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sd a0,CTE_OFFSET_a0(a5); \
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sd a1,CTE_OFFSET_a1(a5); \
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sd a2,CTE_OFFSET_a2(a5); \
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sd a3,CTE_OFFSET_a3(a5); \
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sd v0,CTE_OFFSET_v0(a5); \
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sd v1,CTE_OFFSET_v1(a5);
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#endif /* _LANGUAGE_ASSEMBLY */
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#endif /* _CACHE_H_ */
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