180 lines
4.0 KiB
C
180 lines
4.0 KiB
C
#include <sys/types.h>
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#include <sys/cpu.h>
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#include <sys/sbd.h>
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#include <libsk.h>
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#include "nvram.h"
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static volatile unsigned char *ser_wr_reg =
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(unsigned char *) PHYS_TO_K1( CPU_AUX_CONTROL );
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static volatile unsigned char *ser_rd_reg =
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(unsigned char *) PHYS_TO_K1( CPU_AUX_CONTROL );
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#define SERDATA_OUT CPU_TO_SER /* out of cpu to nvram */
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#define SERDATA_IN SER_TO_CPU /* into cpu from nvram */
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#define RESET_AUXSERCLK *cpu_auxctl &= ~SERCLK
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#define SET_AUXSERCLK *cpu_auxctl |= SERCLK
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#define RESET_PRE *cpu_auxctl &= ~NVRAM_PRE
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#define SET_PRE *cpu_auxctl |= NVRAM_PRE
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void nvram_cs_on(void);
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void nvram_cs_off(void);
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/*
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find out number of address bits in the nvram. since this routine will be
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called from unix, any reference to prom BSS MUST be avoided
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*/
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int
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size_nvram (void)
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{
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int bit_in_command;
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register int i;
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register volatile unsigned char *cpu_auxctl = (unsigned char *)
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PHYS_TO_K1(CPU_AUX_CONTROL);
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unsigned char health_led_off = *cpu_auxctl & LED_GREEN;
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RESET_PRE;
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nvram_cs_on ();
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/*
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shift in read command. assume 3 bits opcode, 6 bits address
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*/
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for (i = 0; i < 9; i++) {
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if ((SER_READ << i) & 0x80000000)
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*ser_wr_reg |= SERDATA_OUT;
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else
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*ser_wr_reg &= ~SERDATA_OUT;
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RESET_AUXSERCLK;
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SET_AUXSERCLK;
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} /* for */
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if (*ser_rd_reg & SERDATA_IN) {
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bit_in_command = 11;
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*ser_wr_reg &= ~SERDATA_OUT;
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RESET_AUXSERCLK;
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SET_AUXSERCLK;
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RESET_AUXSERCLK;
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SET_AUXSERCLK;
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}
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else
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bit_in_command = 9;
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/*
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shift out garbage data
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*/
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for (i = 0; i < 16; i++) {
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RESET_AUXSERCLK;
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SET_AUXSERCLK;
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} /* for */
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nvram_cs_off ();
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*cpu_auxctl = (*cpu_auxctl & ~LED_GREEN) | health_led_off;
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#ifndef LATER
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return(11);
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#else
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return (bit_in_command);
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#endif
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} /* size_nvram */
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/*
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* clock in the nvram command and the register number. For the
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* natl semi conducter nv ram chip the op code is 3 bits and
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* the address is 6/8 bits.
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*/
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void
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nvram_cmd(unsigned int cmd, unsigned int reg, register int bit_in_command)
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{
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ushort ser_cmd;
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int i;
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volatile unsigned char *cpu_auxctl =
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(unsigned char *)PHYS_TO_K1(CPU_AUX_CONTROL);
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ser_cmd = cmd | (reg << (16 - bit_in_command)); /* left justified */
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for (i = 0; i < bit_in_command; i++) {
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if (ser_cmd & 0x8000) /* if high order bit set */
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*ser_wr_reg |= SERDATA_OUT;
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else
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*ser_wr_reg &= ~SERDATA_OUT;
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RESET_AUXSERCLK;
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SET_AUXSERCLK;
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ser_cmd <<= 1;
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}
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*ser_wr_reg &= ~SERDATA_OUT; /* see data sheet timing diagram */
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}
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/*
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* after write/erase commands, we must wait for the command to complete
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* write cycle time is 10 ms max (~5 ms nom); we timeout after ~20 ms
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* NVDELAY_TIME * NVDELAY_LIMIT = 20 ms
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*/
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#define NVDELAY_TIME 100 /* 100 us delay times */
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#define NVDELAY_LIMIT 200 /* 200 delay limit */
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int
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nvram_hold(void)
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{
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int error;
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int timeout = NVDELAY_LIMIT;
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nvram_cs_on();
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while (!(*ser_rd_reg & SERDATA_IN) && timeout--)
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us_delay(NVDELAY_TIME);
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if (!(*ser_rd_reg & SERDATA_IN))
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error = -1;
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else
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error = 0;
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nvram_cs_off();
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return (error);
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}
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/*
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* the version of nvram_cs_on() and nvram_cs_off() we have here is slightly
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* different than the one in stand/saio/ml/IP12.c.
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* THEY ARE NOT INTERCHANGEABLE
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*/
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/*
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* enable the serial memory by setting the console chip select
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*/
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void
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nvram_cs_on(void)
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{
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volatile unsigned char *cpu_auxctl =
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(unsigned char *)PHYS_TO_K1(CPU_AUX_CONTROL);
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unsigned char cs_on;
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int delaylen = 100;
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cs_on = *cpu_auxctl & ~(SERCLK | CONSOLE_CS);
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*cpu_auxctl &= ~CPU_TO_SER; /* see data sheet timing diagram */
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RESET_AUXSERCLK;
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*cpu_auxctl = cs_on;
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while (--delaylen)
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;
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*cpu_auxctl = cs_on | CONSOLE_CS;
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SET_AUXSERCLK;
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}
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/*
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* turn off the chip select
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*/
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void
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nvram_cs_off(void)
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{
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volatile unsigned char *cpu_auxctl =
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(unsigned char *)PHYS_TO_K1(CPU_AUX_CONTROL);
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unsigned char cs_off;
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cs_off = *cpu_auxctl & ~(SERCLK | CONSOLE_CS);
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RESET_AUXSERCLK;
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*cpu_auxctl = cs_off;
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SET_AUXSERCLK;
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}
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