632 lines
11 KiB
ArmAsm
632 lines
11 KiB
ArmAsm
/*
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* prims/vec.s
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*
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*
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* Copyright 1991, Silicon Graphics, Inc.
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* All Rights Reserved.
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*
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* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics, Inc.;
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* the contents of this file may not be disclosed to third parties, copied or
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* duplicated in any form, in whole or in part, without the prior written
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* permission of Silicon Graphics, Inc.
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*
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* RESTRICTED RIGHTS LEGEND:
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* Use, duplication or disclosure by the Government is subject to restrictions
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* as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
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* and Computer Software clause at DFARS 252.227-7013, and/or in similar or
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* successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
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* rights reserved under the Copyright Laws of the United States.
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*/
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#ident "$Revision: 1.7 $"
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#include <asm.h>
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#include <regdef.h>
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#include <cp0.h>
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#include <fault.h>
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/* #include <sys/ip5.h> */
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#include <sys/cpu.h>
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#include <sys/loaddrs.h>
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#include <sys/fpu.h>
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#include <sys/sbd.h>
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#include <saioctl.h>
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#include "pon.h"
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/* #include "mp.h" */
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#define GETREGS \
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li k0,PHYS_TO_K1(EV_SPNUM); \
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lw k0,0(k0); \
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and k0,MPSR_IDMASK; \
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sll k0,9; \
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la k1,_regs; \
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addu k1,k0
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#ifndef pon
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#define LONGWAIT 400000
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#define SHORTWAIT 100000
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#define ALLLEDSLIT 0x3F
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#define ALLLEDSOUT 0x00
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# FastFlash blinks all the LEDs on and off rapid rate (about 1/4 second);
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# ShortWait provides a delay-loop of approximately 1/4 second when running
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# from prom.
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/*
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LEAF(FastFlash)
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move t8,ra # save our return address
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li t9,10 # flash 'em for about 5 secs
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move v1,a0 # save LED error value to write
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2: li a0, ALLLEDSOUT # so turn the LEDS off
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jal set_leds # write to the CPU LEDS
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li v0,SHORTWAIT # get the delay count
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1: addiu v0,v0,-1 # decrement the count
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bgtz v0,1b # spin till it be 0
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move a0,v1 # now show LED error value
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jal set_leds # write to the CPU LEDS
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li v0,SHORTWAIT # get the delay count
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1: addiu v0,v0,-1 # decrement the count
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bgtz v0,1b # spin till it be 0
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addiu t9,t9,-1 # decrement the loop-counter
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bgtz t9,2b # keep on flashin'
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j t8 # and back to the caller
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END(FastFlash)
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*/
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#endif
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LEAF( UpdateCause )
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.set noreorder
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mfc0 v0,C0_CAUSE
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NOP_1_3
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.set reorder
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and a1,v0
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or a0,a1
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.set noreorder
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mtc0 a0,C0_CAUSE
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nop
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.set reorder
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j ra
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.end UpdateCause
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/*
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* save_state -- save all of registers so we can resume to the
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* same execution point.
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*/
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/*
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LEAF(save_state)
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.set noat
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move k0,AT
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.set at
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GETREGS
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sw k0,EF_AT*4(k1)
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sw v0,EF_V0*4(k1)
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.set noreorder
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mfc0 v0,C0_EPC
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NOP_1_3
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sw v0,EF_EPC*4(k1)
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mfc0 v0,C0_SR
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NOP_1_3
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sw v0,EF_SR*4(k1)
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mfc0 v0,C0_BADVADDR
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NOP_1_3
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sw v0,EF_BADVADDR*4(k1)
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mfc0 v0,C0_CAUSE
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NOP_1_3
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sw v0,EF_CAUSE*4(k1)
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.set reorder
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sw sp,EF_SP*4(k1)
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li v0,EV_SPNUM
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lw v0,0(v0)
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sw v0,EF_MPSR*4(k1)
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lw v0,EF_EPC*4(k1)
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sw v0,R_EPC*4(k1)
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lw v0,EF_SR*4(k1)
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sw v0,R_SR*4(k1)
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lw v0,EF_AT*4(k1)
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sw v0,R_AT*4(k1)
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lw v0,EF_V0*4(k1)
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sw v0,R_V0*4(k1)
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lw v0,EF_EXC*4(k1)
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sw v0,R_EXCTYPE*4(k1)
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lw v0,EF_BADVADDR*4(k1)
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sw v0,R_BADVADDR*4(k1)
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lw v0,EF_CAUSE*4(k1)
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sw v0,R_CAUSE*4(k1)
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lw v0,EF_SP*4(k1)
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sw v0,R_SP*4(k1)
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sw zero,R_ZERO*4(k1) # we don't trust anything
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sw v1,R_V1*4(k1)
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sw a0,R_A0*4(k1)
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sw a1,R_A1*4(k1)
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sw a2,R_A2*4(k1)
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sw a3,R_A3*4(k1)
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sw t0,R_T0*4(k1)
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sw t1,R_T1*4(k1)
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sw t2,R_T2*4(k1)
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sw t3,R_T3*4(k1)
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sw t4,R_T4*4(k1)
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sw t5,R_T5*4(k1)
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sw t6,R_T6*4(k1)
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sw t7,R_T7*4(k1)
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sw s0,R_S0*4(k1)
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sw s1,R_S1*4(k1)
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sw s2,R_S2*4(k1)
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sw s3,R_S3*4(k1)
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sw s4,R_S4*4(k1)
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sw s5,R_S5*4(k1)
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sw s6,R_S6*4(k1)
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sw s7,R_S7*4(k1)
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sw t8,R_T8*4(k1)
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sw t9,R_T9*4(k1)
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li k0,0xbad00bad # make it obvious we can't save this
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sw k0,R_K0*4(k1)
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sw k1,R_K1*4(k1)
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sw fp,R_FP*4(k1)
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sw gp,R_GP*4(k1)
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sw ra,R_RA*4(k1)
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mflo v0
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sw v0,R_MDLO*4(k1)
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mfhi v0
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sw v0,R_MDHI*4(k1)
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.set noreorder
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mfc0 v0,C0_INX
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NOP_1_3
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sw v0,R_INX*4(k1)
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NOP_1_3
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mfc0 v0,C0_RAND # save just to see it change
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NOP_1_3
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sw v0,R_RAND*4(k1)
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NOP_1_3
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mfc0 v0,C0_TLBLO
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NOP_1_3
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sw v0,R_TLBLO*4(k1)
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NOP_1_3
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mfc0 v0,C0_TLBHI
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NOP_1_3
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sw v0,R_TLBHI*4(k1)
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NOP_1_3
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mfc0 v0,C0_CTXT
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NOP_1_3
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sw v0,R_CTXT*4(k1)
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NOP_1_3
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# now save the R4K-specific cp0 regs
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mfc0 v0,C0_TLBLO_1
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NOP_1_3
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sw v0,R_TLBLO1*4(k1)
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NOP_1_3
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mfc0 v0,C0_PGMASK
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NOP_1_3
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sw v0,R_PGMSK*4(k1)
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NOP_1_3
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mfc0 v0,C0_TLBWIRED
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NOP_1_3
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sw v0,R_WIRED*4(k1)
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NOP_1_3
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mfc0 v0,C0_COUNT
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NOP_1_3
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sw v0,R_COUNT*4(k1)
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NOP_1_3
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mfc0 v0,C0_COMPARE
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NOP_1_3
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sw v0,R_COMPARE*4(k1)
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NOP_1_3
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mfc0 v0,C0_CONFIG
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NOP_1_3
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sw v0,R_CONFIG*4(k1)
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NOP_1_3
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mfc0 v0,C0_LLADDR
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NOP_1_3
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sw v0,R_LLADDR*4(k1)
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NOP_1_3
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mfc0 v0,C0_WATCHLO
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NOP_1_3
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sw v0,R_WATCHLO*4(k1)
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NOP_1_3
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mfc0 v0,C0_WATCHHI
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NOP_1_3
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sw v0,R_WATCHHI*4(k1)
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NOP_1_3
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mfc0 v0,C0_ECC
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NOP_1_3
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sw v0,R_ECC*4(k1)
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NOP_1_3
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mfc0 v0,C0_CACHE_ERR
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NOP_1_3
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sw v0,R_CACHERR*4(k1)
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NOP_1_3
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mfc0 v0,C0_TAGLO
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NOP_1_3
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sw v0,R_TAGLO*4(k1)
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NOP_1_3
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mfc0 v0,C0_TAGHI
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NOP_1_3
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sw v0,R_TAGHI*4(k1)
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NOP_1_3
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mfc0 v0,C0_ERROR_EPC
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NOP_1_3
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sw v0,R_ERREPC*4(k1)
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NOP_1_3
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.set reorder
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lw v0,EF_SR*4(k1)
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and v0,SR_CU1
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beq v0,zero,nosave
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swc1 $f0,R_F0*4(k1)
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swc1 $f1,R_F1*4(k1)
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swc1 $f2,R_F2*4(k1)
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swc1 $f3,R_F3*4(k1)
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swc1 $f4,R_F4*4(k1)
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swc1 $f5,R_F5*4(k1)
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swc1 $f6,R_F6*4(k1)
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swc1 $f7,R_F7*4(k1)
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swc1 $f8,R_F8*4(k1)
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swc1 $f9,R_F9*4(k1)
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swc1 $f10,R_F10*4(k1)
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swc1 $f11,R_F11*4(k1)
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swc1 $f12,R_F12*4(k1)
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swc1 $f13,R_F13*4(k1)
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swc1 $f14,R_F14*4(k1)
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swc1 $f15,R_F15*4(k1)
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swc1 $f16,R_F16*4(k1)
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swc1 $f17,R_F17*4(k1)
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swc1 $f18,R_F18*4(k1)
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swc1 $f19,R_F19*4(k1)
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swc1 $f20,R_F20*4(k1)
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swc1 $f21,R_F21*4(k1)
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swc1 $f22,R_F22*4(k1)
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swc1 $f23,R_F23*4(k1)
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swc1 $f24,R_F24*4(k1)
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swc1 $f25,R_F25*4(k1)
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swc1 $f26,R_F26*4(k1)
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swc1 $f27,R_F27*4(k1)
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swc1 $f28,R_F28*4(k1)
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swc1 $f29,R_F29*4(k1)
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swc1 $f30,R_F30*4(k1)
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swc1 $f31,R_F31*4(k1)
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cfc1 v0,$30
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sw v0,R_C1_EIR*4(k1)
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cfc1 v0,$31
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sw v0,R_C1_SR*4(k1)
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nosave:
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j ra
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END(save_state)
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*/
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/*
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* restore_state -- resume execution of mainline code
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*/
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/*
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#include "ml.h"
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LEAF(restore_state)
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GETREGS
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lw v0,R_SR*4(k1)
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and v0,SR_CU1
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beq v0,zero,1f
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.set noreorder
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mtc0 v0,C0_SR
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.set reorder
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lwc1 $f0,R_F0*4(k1)
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lwc1 $f1,R_F1*4(k1)
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lwc1 $f2,R_F2*4(k1)
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lwc1 $f3,R_F3*4(k1)
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lwc1 $f4,R_F4*4(k1)
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lwc1 $f5,R_F5*4(k1)
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lwc1 $f6,R_F6*4(k1)
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lwc1 $f7,R_F7*4(k1)
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lwc1 $f8,R_F8*4(k1)
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lwc1 $f9,R_F9*4(k1)
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lwc1 $f10,R_F10*4(k1)
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lwc1 $f11,R_F11*4(k1)
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lwc1 $f12,R_F12*4(k1)
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lwc1 $f13,R_F13*4(k1)
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lwc1 $f14,R_F14*4(k1)
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lwc1 $f15,R_F15*4(k1)
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lwc1 $f16,R_F16*4(k1)
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lwc1 $f17,R_F17*4(k1)
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lwc1 $f18,R_F18*4(k1)
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lwc1 $f19,R_F19*4(k1)
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lwc1 $f20,R_F20*4(k1)
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lwc1 $f21,R_F21*4(k1)
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lwc1 $f22,R_F22*4(k1)
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lwc1 $f23,R_F23*4(k1)
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lwc1 $f24,R_F24*4(k1)
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lwc1 $f25,R_F25*4(k1)
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lwc1 $f26,R_F26*4(k1)
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lwc1 $f27,R_F27*4(k1)
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lwc1 $f28,R_F28*4(k1)
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lwc1 $f29,R_F29*4(k1)
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lwc1 $f30,R_F30*4(k1)
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lwc1 $f31,R_F31*4(k1)
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lw v0,R_C1_EIR*4(k1)
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ctc1 v0,$30
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lw v0,R_C1_SR*4(k1)
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ctc1 v0,$31
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1:
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lw a0,R_A0*4(k1)
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lw a1,R_A1*4(k1)
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lw a2,R_A2*4(k1)
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lw a3,R_A3*4(k1)
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lw t0,R_T0*4(k1)
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lw t1,R_T1*4(k1)
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lw t2,R_T2*4(k1)
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lw t3,R_T3*4(k1)
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lw t4,R_T4*4(k1)
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lw t5,R_T5*4(k1)
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lw t6,R_T6*4(k1)
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lw t7,R_T7*4(k1)
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lw s0,R_S0*4(k1)
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lw s1,R_S1*4(k1)
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lw s2,R_S2*4(k1)
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lw s3,R_S3*4(k1)
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lw s4,R_S4*4(k1)
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lw s5,R_S5*4(k1)
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lw s6,R_S6*4(k1)
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lw s7,R_S7*4(k1)
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lw t8,R_T8*4(k1)
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lw t9,R_T9*4(k1)
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lw k1,R_K1*4(k1)
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lw gp,R_GP*4(k1)
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lw fp,R_FP*4(k1)
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lw ra,R_RA*4(k1)
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lw v0,R_MDLO*4(k1)
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mtlo v0
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lw v1,R_MDHI*4(k1)
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mthi v1
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.set noreorder
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lw v0,R_INX*4(k1)
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NOP_1_3
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mtc0 v0,C0_INX
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NOP_1_3
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lw v1,R_TLBLO*4(k1)
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NOP_1_3
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TLBLO_FIX_250MHz(C0_TLBLO) # 250MHz R4K workaround
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mtc0 v1,C0_TLBLO
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NOP_1_3
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lw v0,R_TLBHI*4(k1)
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NOP_1_3
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mtc0 v0,C0_TLBHI
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NOP_1_3
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lw v1,R_CTXT*4(k1)
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NOP_1_3
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mtc0 v1,C0_CTXT
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NOP_1_3
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lw v0,R_CAUSE*4(k1)
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NOP_1_3
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mtc0 v0,C0_CAUSE # for software interrupts
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# add R4K-specific regs now
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lw v0,R_TLBLO1*4(k1)
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NOP_1_3
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TLBLO_FIX_250MHz(C0_TLBLO_1) # 250MHz R4K workaround
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mtc0 v0,C0_TLBLO_1
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lw v1,R_PGMSK*4(k1)
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NOP_1_3
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mtc0 v1,C0_PGMASK
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NOP_1_3
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lw v0,R_WIRED*4(k1)
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NOP_1_3
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mtc0 v0,C0_TLBWIRED
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NOP_1_3
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lw v0,R_COMPARE*4(k1)
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NOP_1_3
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mtc0 v0,C0_COMPARE
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NOP_1_3
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lw v1,R_WATCHLO*4(k1)
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NOP_1_3
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mtc0 v1,C0_WATCHLO
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NOP_1_3
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lw v0,R_WATCHHI*4(k1)
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NOP_1_3
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mtc0 v0,C0_WATCHHI
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NOP_1_3
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lw v1,R_TAGLO*4(k1)
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NOP_1_3
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mtc0 v1,C0_TAGLO
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NOP_1_3
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lw v0,R_SR*4(k1)
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NOP_1_3
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mtc0 v0,C0_SR
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NOP_1_4
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NOP_1_4
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.set reorder
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lw sp,R_SP*4(k1)
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lw v0,R_V0*4(k1)
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lw v1,R_V1*4(k1)
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addiu ra,8
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.set noat
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.set noreorder
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lw AT,R_AT*4(k1)
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j ra
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.set reorder
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.set at
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END(restore_state)
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*/
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LEAF(newstack)
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#if _MIPS_SIM == _ABI64
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addu a3,a0,a1 # base of new stack
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#else
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addu t5,a0,a1 # base of new stack
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#endif
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li t0,6 # save 5 words of stack, + old sp
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sll t0,t0,2 # number of bytes
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#if _MIPS_SIM == _ABI64
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subu t2,a3,t0 # start for copy
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move a4,t2 # save new sp
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#else
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subu t2,t5,t0 # start for copy
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move t6,t2 # save new sp
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#endif
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addu t1,t0,sp # copy end address
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move t3,sp # copy start address
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#if _MIPS_SIM == _ABI64
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sw sp,(a3) # save old sp
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loop:
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lw a2,(t3) # get a word
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#else
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sw sp,(t5) # save old sp
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loop:
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lw t4,(t3) # get a word
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#endif
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addiu t3,t3,4 # bump count
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#if _MIPS_SIM == _ABI64
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sw a2,(t2) # store the word
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#else
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sw t4,(t2) # store the word
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#endif
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addiu t2,t2,4 # and bump the destination count
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blt t3,t1,loop # do it again
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#if _MIPS_SIM == _ABI64
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move sp,a4 # set top of new stack
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move fp,a4 # set new frame
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#else
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move sp,t6 # set top of new stack
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move fp,t6 # set new frame
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#endif
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j ra # back to caller
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END(newstack)
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LEAF(oldstack)
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#if _MIPS_SIM == _ABI64
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addu a3,a0,a1 # base of new stack
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lw sp,(a3) # get back old sp
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#else
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addu t5,a0,a1 # base of new stack
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lw sp,(t5) # get back old sp
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#endif
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move fp,sp # get back old frame
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j ra # back to caller
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END(oldstack)
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LEAF(runcached)
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subu v0,ra,K0SIZE
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1: j v0
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END(runcached)
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LEAF(uncached)
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addu v0,ra,K0SIZE
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1: j v0
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END(uncached)
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LEAF( DoExceptionEret )
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.set noreorder
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mtc0 ra,C0_EPC
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nop
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nop
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nop
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eret
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.set reorder
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END(DoExceptionEret)
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LEAF( DoErrorEret )
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.set noreorder
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dmtc0 ra,C0_EPC
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nop
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nop
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nop
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eret
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.set reorder
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END(DoErrorEret)
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/* sd_hitinv(vaddr): Secondary Data cache HIT INValidate.
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* invalidates secondary and primary cache blocks if virtual address is valid
|
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* a0: virtual address to invalidate if present */
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LEAF(sd_hitinv)
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.set noreorder
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#ifdef TFP
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DMTC0(t1,C0_BADVADDR)
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DMTC0(zero,C0_DCACHE) # clear all (4) Valid bits
|
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dctw # write to the Dcache Tag
|
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ssnop; ssnop; ssnop # pipeline hazard prevention
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#else
|
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cache CACH_SD|C_HINV, 0(a0)
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#endif
|
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nop
|
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nop
|
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j ra
|
|
nop
|
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.set reorder
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END(sd_hitinv)
|
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|
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LEAF(get_count)
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.set noreorder
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mfc0 v0,C0_COUNT
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nop
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j ra
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nop
|
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.set reorder
|
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END(get_count)
|
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LEAF(set_count)
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.set noreorder
|
|
mtc0 a0,C0_COUNT
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nop
|
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.set reorder
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j ra
|
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END(set_count)
|
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LEAF(get_compare)
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.set noreorder
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#ifndef TFP
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mfc0 v0,C0_COMPARE
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nop
|
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#endif
|
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j ra
|
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nop
|
|
.set reorder
|
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END(get_compare)
|
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|
|
/* side effect of setting compare register: clears the timer interrupt */
|
|
LEAF(set_compare)
|
|
.set noreorder
|
|
#ifndef TFP
|
|
mtc0 a0,C0_COMPARE
|
|
nop
|
|
#endif
|
|
.set reorder
|
|
j ra
|
|
END(set_compare)
|
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