calmsacibis995
81 lines
2.5 KiB
Plaintext
81 lines
2.5 KiB
Plaintext
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RADICAL IDE COMMANDS
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The following is the list of commands available to use IDE
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====================================COMMANDS=========================
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rad_regs rad_dma rad_ram rad_all_cards radical
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shoebox_all shoebox
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Description of Commands and how to use them
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================================================================================
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The following individual operations can be run:
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rad_regs
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---------
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Performs write/read/verify tests on all rad registers.
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Data flows from main memory, to heart, to xbow, to bridge, to rad chip registers
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Usage: rad_regs [-s1|2|3]
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Default: tests IP30 rad chip
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Options: specify slot # in pci shoebox
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-s1 tests radical card 1
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-s2 tests radical card 2
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-s3 tests radical card 3
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rad_dma
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---------
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Perform status dma from chip to memory, and verifies that DMA was done
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Data flows from main memory, to heart, to xbow, to bridge, to rad dma registers
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Usage: rad_dma [-s1|2|3]
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Default and options same as in rad_regs test
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rad_ram
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---------
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Performs write/read/verify tests on dma registers
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Data flows from main memory, to heart, to xbow, to bridge, to rad ram
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Usage: rad_ram [-s1|2|3]
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Default and options same as in rad_regs test
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rad_all_cards
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-------------
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Runs all radical tests on one specified card.
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Usage: rad_all_cards [-s1|2|3]
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Default and options same as in rad_regs test
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radical
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---------
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Tests all cards running all rad tests. Boots unix if tests passes
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shoebox_all
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-----------
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Runs the following bridge tests:
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br_regs
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------
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Performs write/read/verify tests. The register contents are saved.
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Then a pattern is written. It is read back and verified. The contents
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of the register are restored on exit.
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Data flows from main memory, to heart, to xbow, to bridge registers
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br_ram
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------
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Tests built in bridge memory. Performs write/read/verify tests. A
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pattern is written to memory. It is read back and verified.
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Data flows from main memory, to heart, to xbow, to bridge ram
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br_intr
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-------
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A bridge interrupt is generated by writing the INTR bit. The test then
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verifies that the interrupt occurred
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Data flows from main memory, to heart, to xbow, to bridge intr registers
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br_err
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-------
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This test the ability of the bridge to generate errors when writing to a bad bridge
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address. Errors are created by writing to invalid addresses. The test verifies that
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bridge caught the error.
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Data flows from main memory, to heart, to xbow, to bridge err registers
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shoebox
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-------
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Runs all bridge tests documented above (in shoebox_all) and boots unix if they passed
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