108 lines
4.5 KiB
C
108 lines
4.5 KiB
C
/*
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* gz_errorcodes.c - Godzilla errorcodes
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*
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* Copyright 1997, Silicon Graphics, Inc.
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* ALL RIGHTS RESERVED
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*
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* UNPUBLISHED -- Rights reserved under the copyright laws of the United
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* States. Use of a copyright notice is precautionary only and does not
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* imply publication or disclosure.
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*
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* U.S. GOVERNMENT RESTRICTED RIGHTS LEGEND:
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* Use, duplication or disclosure by the Government is subject to restrictions
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* as set forth in FAR 52.227.19(c)(2) or subparagraph (c)(1)(ii) of the Rights
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* in Technical Data and Computer Software clause at DFARS 252.227-7013 and/or
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* in similar or successor clauses in the FAR, or the DOD or NASA FAR
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* Supplement. Contractor/manufacturer is Silicon Graphics, Inc.,
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* 2011 N. Shoreline Blvd. Mountain View, CA 94039-7311.
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*
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* THE CONTENT OF THIS WORK CONTAINS CONFIDENTIAL AND PROPRIETARY
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* INFORMATION OF SILICON GRAPHICS, INC. ANY DUPLICATION, MODIFICATION,
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* DISTRIBUTION, OR DISCLOSURE IN ANY FORM, IN WHOLE, OR IN PART, IS STRICTLY
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* PROHIBITED WITHOUT THE PRIOR EXPRESS WRITTEN PERMISSION OF SILICON
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* GRAPHICS, INC.
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*
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* These errorcodes will be used in the ide tests for the godzilla
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* architecture.
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*/
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#include "sys/cpu.h"
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#include "uif.h"
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#include "d_godzilla.h"
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#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
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_Test_Info CPU_Test_err[] = {
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{ "Bridge Error", "BDG001" },
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{ "Bridge Interrupt", "BDG002" },
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{ "Bridge Bridge Internal/External RAM", "BDG003" },
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{ "Bridge Read-Write Register", "BDG004" },
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{ "Bridge Check Out", "BDG101" },
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{ "Bridge Reset", "BDG105" },
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{ "ECC", "ECC001" },
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{ "ENET Tests", "ETH001" },
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{ "ENET External Loopback", "ETH002" },
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{ "ENET Stress", "ETH003" },
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{ "Heart, Xbow & Bridge Check Out", "HXB001" },
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{ "Heart, Xbow & Bridge Save Register", "HXB002" },
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{ "Heart, Xbow & Bridge Restore Register", "HXB003" },
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{ "Heart Interrupt Registers", "HRT001" },
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{ "Heart Miscellaneous Registers", "HRT002" },
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{ "Heart PIO Access", "HRT003" },
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{ "Heart PIU Access", "HRT004" },
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{ "Heart Read-Write Register", "HRT005" },
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{ "Heart Check Out", "HRT101" },
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{ "Heart Reset", "HRT104" },
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{ "Heart & Bridge Check Out", "HAB101" },
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{ "Heart & Bridge Save Registers", "HAB102" },
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{ "Heart & Bridge Restore Registers", "HAB103" },
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{ "Heart & Bridge Reset", "HAB106" },
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{ "IOC3 DUART Read-Write Register", "IOC301" },
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{ "IOC3 Read-Write Register", "IOC302" },
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{ "IOC3 SRAM", "IOC303" },
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{ "RTC Read-Write Register", "RTC001" },
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{ "Memory", "MEM001" },
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{ "PCI Configuration Read", "PCI001" },
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{ "PCI Configuration Write", "PCI002" },
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{ "PCI Interrupt", "PCI003" },
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{ "PCI Memory Space", "PCI004" },
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{ "PCI Parallel Port", "PCI005" },
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{ "PCI Real Time Clock", "PCI006" },
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{ "PCI Serial Port", "PCI007" },
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{ "PCI Parallel Port Loopback", "PCI008" },
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{ "PCI Shoebox All Tests", "PCI101" },
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{ "RAD All Tests", "RAD001" },
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{ "RAD Configuration Space", "RAD002" },
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{ "RAD RAM", "RAD003" },
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{ "RAD Status DMA", "RAD103" },
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{ "SCSI QLOGIC Controller", "SCS101" },
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{ "SCSI Read-Write Register", "SCS102" },
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{ "Heart/Xbow Bad LLP", "HXB101" },
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{ "Xbow Access", "XBO101" },
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{ "Xbow Read-Write Register", "XBO102" },
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{ NULL, NULL }
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};
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#endif /* C || C++ */
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