493 lines
16 KiB
C
493 lines
16 KiB
C
#ifndef __SYS_R10K_H__
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#define __SYS_R10K_H__
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/**************************************************************************
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* *
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* Copyright (C) 1994, Silicon Graphics, Inc. *
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* *
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* These coded instructions, statements, and computer programs contain *
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* unpublished proprietary information of Silicon Graphics, Inc., and *
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* are protected by Federal copyright law. They may not be disclosed *
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* to third parties or copied or duplicated in any form, in whole or *
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* in part, without the prior written consent of Silicon Graphics, Inc. *
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* *
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**************************************************************************/
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#ident "$Revision: 1.1 $"
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#if defined(_LANGUAGE_C)
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#include <sys/types.h> /* needed for cacheop_t */
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#endif
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/*
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* Coprocessor 0 registers
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* Some of these are r4000 specific.
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*/
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#ifdef _LANGUAGE_ASSEMBLY
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#define C0_INX $0
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#define C0_RAND $1
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#define C0_TLBLO_0 $2
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#define C0_TLBLO_1 $3
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#define C0_CTXT $4
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#define C0_PGMASK $5 /* page mask */
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#define C0_TLBWIRED $6 /* # wired entries in tlb */
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#define C0_COUNT $9 /* free-running counter */
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#define C0_BADVADDR $8
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#define C0_TLBHI $10
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#define C0_COMPARE $11 /* counter comparison reg. */
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#define C0_SR $12
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#define C0_CAUSE $13
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#define C0_EPC $14
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#define C0_PRID $15 /* revision identifier */
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#define C0_CONFIG $16 /* hardware configuration */
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#define C0_LLADDR $17 /* load linked address */
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#define C0_WATCHLO $18 /* watchpoint */
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#define C0_WATCHHI $19 /* watchpoint */
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#define C0_EXTCTXT $20 /* Extended context */
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#define C0_FMMASK $21 /* Frame Mask */
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#define C0_BRDIAG $22 /* Indices of tlb wired entries */
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#define C0_PRFCNT0 $25 /* performance counter 0 */
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#define C0_PRFCNT1 $25 /* performance counter 1 */
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#define C0_PRFCRTL0 $25 /* performance control reg 0 */
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#define C0_PRFCRTL1 $25 /* performance control reg 1 */
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#define C0_ECC $26 /* S-cache ECC and primary parity */
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#define C0_CACHE_ERR $27 /* cache error status */
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#define C0_TAGLO $28 /* cache operations */
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#define C0_TAGHI $29 /* cache operations */
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#define C0_ERROR_EPC $30 /* ECC error prg. counter */
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# else /* ! _LANGUAGE_ASSEMBLY */
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#define C0_INX 0
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#define C0_RAND 1
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#define C0_TLBLO_0 2
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#define C0_TLBLO_1 3
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#define C0_CTXT 4
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#define C0_PGMASK 5 /* page mask */
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#define C0_TLBWIRED 6 /* # wired entries in tlb */
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#define C0_BADVADDR 8
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#define C0_COUNT 9 /* free-running counter */
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#define C0_TLBHI 10
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#define C0_COMPARE 11 /* counter comparison reg. */
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#define C0_SR 12
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#define C0_CAUSE 13
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#define C0_EPC 14
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#define C0_PRID 15 /* revision identifier */
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#define C0_CONFIG 16 /* hardware configuration */
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#define C0_LLADDR 17 /* load linked address */
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#define C0_WATCHLO 18 /* watchpoint */
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#define C0_WATCHHI 19 /* watchpoint */
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#define C0_EXTCTXT 20 /* Extended context */
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#define C0_FMMASK 21 /* Frame Mask */
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#define C0_BRDIAG 22 /* Indices of tlb wired entries */
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#define C0_PRFCNT0 25 /* performance counter 0 */
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#define C0_PRFCNT1 25 /* performance counter 1 */
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#define C0_PRFCRTL0 25 /* performance control reg 0 */
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#define C0_PRFCRTL1 25 /* performance control reg 1 */
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#define C0_ECC 26 /* S-cache ECC and primary parity */
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#define C0_CACHE_ERR 27 /* cache error status */
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#define C0_TAGLO 28 /* cache operations */
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#define C0_TAGHI 29 /* cache operations */
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#define C0_ERROR_EPC 30 /* ECC error prg. counter */
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#endif /* _LANGUAGE_ASSEMBLY */
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/*
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* R10k Config Register defines.
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*/
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#define CONFIG_IC 0xe0000000 /* primary instruction cache size */
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#define CONFIG_IC_SHFT 29
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#define CONFIG_DC 0x1c000000 /* primary data cache size */
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#define CONFIG_DC_SHFT 26
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#define CONFIG_SC 0x00380000 /* Secondary cache clock ratio */
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#define CONFIG_SC_SHFT 19
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#define CONFIG_SS 0x00070000 /* secondary cache size */
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#define CONFIG_SS_SHFT 16
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#define CONFIG_BE 0x00008000 /* Memory/kernel Endianness */
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#define CONFIG_BE_SHFT 15
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#define CONFIG_SK 0x00004000 /* Correbcting sec. data ECC err */
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#define CONFIG_SB 0x00002000 /* Secondary cache block size 16/32 */
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#define CONFIG_SB_SHFT 13
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#define CONFIG_EC 0x00001e00 /* System interface clock ratio */
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#define CONFIG_EC_SHFT 9
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#define CONFIG_PM 0x00000180 /* Max outstanding proc requests */
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#define CONFIG_PM_SHFT 7
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#define CONFIG_PE 0x00000040 /* Enable/Disable eliminate req */
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#define CONFIG_CT 0x00000020 /* Target of coherence reqs */
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#define CONFIG_DN 0x00000018 /* Device number */
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#define CONFIG_DN_SHFT 3
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#define CONFIG_K0 0x00000007 /* K0SEG Coherency algorithm */
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#define CONFIG_UNCACHED 0x00000002 /* K0 is uncached */
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#if _RUN_UNCACHED
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#define CONFIG_NONCOHRNT CONFIG_UNCACHED
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#define CONFIG_COHRNT_EXL CONFIG_UNCACHED
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#define CONFIG_COHRNT_EXLWR CONFIG_UNCACHED
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#else
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#define CONFIG_NONCOHRNT 0x00000003
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#define CONFIG_COHRNT_EXL 0x00000004
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#define CONFIG_COHRNT_EXLWR 0x00000005
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#endif /* _RUN_UNCACHED */
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#define CONFIG_UNCACHED_ACC 0x00000007 /* K0 is uncached accelerated */
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#define CONFIG_PCACHE_POW2_BASE 12 /* 2^12+# in config is primary size */
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#define CONFIG_SCACHE_POW2_BASE 19 /* 2^??+# in config is 2ndary size */
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/*
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* R10k Cache Definitions
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* Cache sizes are in bytes
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*/
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#define CACHE_ILINE_SIZE 64 /* Primary instruction line size */
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#define CACHE_ILINE_MASK ~(CACHE_ILINE_SIZE-1)
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#define CACHE_DLINE_SIZE 32 /* Primary data line size */
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#define CACHE_DLINE_MASK ~(CACHE_DLINE_SIZE-1)
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#define CACHE_SLINE_SIZE 128 /* Secondary cache line size */
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#define CACHE_SLINE_MASK ~(CACHE_SLINE_SIZE-1)
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#define CACHE_SLINE_SUBSIZE 16 /* quadword subsize */
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/*
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* Primary Cache Tag Definitions: (64 bits)
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*
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* For cache operations uing TAGLO/TAGHI register, bits 32-63 correspond
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* to TAGHI, 0-31 correspond to TAGLO.
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*
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* Primary Cache Tag:
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*
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* +------+---+--------+--------+-----+---+---+----+------+-----+
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* |St Mod|und|T[35:32]|T[31:12]|State|und|LRU|St P| Set |Tag P|
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* +------+---+--------+--------+-----+---+---+----+------+-----+
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* 6 6 6 3 3 3 3 0 0 0 0 0 0 0 0 0
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* 3 1 0 6 5 2 1 8 7 6 5 4 3 2 1 0
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*
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*/
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#define CTP_TAGPARITY_MASK 0x0000000000000001 /* Tag parity */
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#define CTP_TAGPARITY_SHFT 0
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#define CTP_SCW 0x0000000000000002 /* Secondary cache way */
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#define CTP_STATEPARITY_MASK 0x0000000000000004 /* State parity mask*/
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#define CTP_STATEPARITY_SHFT 2 /* State Parity shift */
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#define CTP_LRU 0x0000000000000008 /* LRU */
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#define CTP_STATE_MASK 0x00000000000000c0 /* state */
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#define CTP_STATE_SHFT 6
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# define CTP_STATE_I 0 /* Invalid */
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# define CTP_STATE_S 1 /* shared */
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# define CTP_STATE_CE 2 /* clean exclusive */
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# define CTP_STATE_DE 3 /* dirty exclusive */
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#define CTP_STATEMOD_SHFT 61
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#define CTP_STATEMOD_MASK (0x7L<<CTP_STATEMOD_SHFT)
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# define CTP_STATEMOD_N 1 /* normal */
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# define CTP_STATEMOD_I 2 /* inconsistent */
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# define CTP_STATEMOD_R 4 /* refill */
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#define CTP_TAG_MASK 0x0000000fffffff00 /* TAG */
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#define CTP_TAG_SHFT 8
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/* Mask of bits that are valid for icache and dcache tags */
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#define CTP_ICACHE_TAG_MASK (CTP_TAGPARITY_MASK+CTP_STATEPARITY_MASK+ \
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CTP_STATEPARITY_MASK+CTP_LRU+CTP_STATE_I+\
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CTP_TAG_MASK+CTP_STATEMOD_MASK)
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#define CTP_DCACHE_TAG_MASK (CTP_TAGPARITY_MASK+CTP_STATEPARITY_MASK+ \
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CTP_STATEPARITY_MASK+CTP_LRU+ \
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CTP_STATE_MASK+CTP_TAG_MASK+ \
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CTP_STATEMOD_MASK)
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#define CTP_ICACHE_TAGHI_MASK 0x0000000f
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#define CTP_ICACHE_TAGLO_MASK 0xffffff4d
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#define CTP_DCACHE_TAGHI_MASK 0xe000000f
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#define CTP_DCACHE_TAGLO_MASK 0xffffffcf
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/*
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* Secondary Cache Tag Definitions: (64 bits)
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*
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* +-----+-----+------------+------------+---+-------+-+----------+-----+
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* | MRU | | TAG[35:32] | TAG[31:18] | | State | | Virt Idx | ECC |
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* +-----+-----+------------+------------+---+-------+-+---------+-----+
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* 6 6 3 3 3 3 1 1 1 1 1 0 0 0 0 0
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* 3 2 6 5 2 1 4 3 2 1 0 9 8 7 6 0
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*/
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#define CTS_MRU 0x8000000000000000
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#define CTS_TAG_MASK 0x0000000fffffc000
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#define CTS_TAG_SHFT 14
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#define CTS_STATE_MASK 0x0000000000000c00
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#define CTS_STATE_SHFT 10
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# define CTS_STATE_I 0 /* Invalid */
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# define CTS_STATE_S 1 /* shared */
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# define CTS_STATE_CE 2 /* clean exclusive */
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# define CTS_STATE_DE 3 /* dirty exclusive */
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#define CTS_VIDX_MASK 0x0000000000000180
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#define CTS_VIDX_SHFT 7
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#define CTS_ECC_MASK 0x000000000000007f
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/* Mask of bits ahat are valid for scache tags */
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#define CTS_MASK (CTS_MRU+CTS_TAG_MASK+CTS_STATE_MASK+ \
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CTS_VIDX_MASK+CTS_ECC_MASK)
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#define CTS_TAGHI_MASK 0x8000000f
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#define CTS_TAGLO_MASK 0xffffcdff
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/* Cache Error Register */
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#define CE_TYPE_SHFT 30 /* Shift for type select */
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#define CE_TYPE_MASK (3U<<CE_TYPE_SHFT)
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#define CE_TYPE_I (0) /* Instruction cache error */
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#define CE_TYPE_D (1U<<CE_TYPE_SHFT)
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#define CE_TYPE_S (2U<<CE_TYPE_SHFT)
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#define CE_TYPE_SIE (3U<<CE_TYPE_SHFT)
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#define CE_EW (1<<29)
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#define CE_EE (1<<28)
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/*
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* Cache Error - data array error/ uncorrectable response error, valid for
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* all cache error types.
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*/
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#define CE_D_WAY1 (1<<27)
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#define CE_D_WAY0 (1<<26)
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#define CE_D_MASK (CE_D_WAY1+CE_D_WAY0)
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/*
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* Cache Error - Tag array error, valid for I-cache, D-cache and
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* S-cache errors.
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*/
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#define CE_TA_WAY1 (1<<25)
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#define CE_TA_WAY0 (1<<24)
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#define CE_TA_MASK (CE_TA_WAY1+CE_TA_WAY0)
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/*
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* Cache Error - Tag state array error, valid for I-cache and D-cache
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* errors.
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*/
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#define CE_TS_WAY1 (1<<23)
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#define CE_TS_WAY0 (1<<22)
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#define CE_TS_MASK (CE_TS_WAY1+CE_TS_WAY0)
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/*
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* Cache Error - Tag mod array error bits, valid only for D-cache errors.
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*/
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#define CE_TM_WAY1 (1<<21)
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#define CE_TM_WAY0 (1<<20)
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#define CE_TM_MASK (CE_TM_WAY1+CE_TM_WAY0)
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/*
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* Cache Error - System interface error defines.
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*/
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#define CE_SA (1<<25)
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#define CE_SC (1<<24)
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#define CE_SR (1<<23)
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/* Cache Error - masks for cache indexes */
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#define CE_SINDX_MASK (0x007fffc0)
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#define CE_PINDX_MASK (0x00003ff8)
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/*
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* C0_CACHE_ERR definitions.
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*/
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#define CACHERR_SRC_MSK CE_TYPE_MASK
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#define CACHERR_SRC_PI CE_TYPE_I
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#define CACHERR_SRC_PD CE_TYPE_D
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#define CACHERR_SRC_SD CE_TYPE_S
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#define CACHERR_SRC_SYSAD CE_TYPE_SIE
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#define CACHERR_EW CE_EW /* multiple errors from the same
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source */
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#define CACHERR_EE CE_EE /* PDcache: tag error on an inconsistent
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block
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SYSAD: data error on a clean/dirty
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exclusive line */
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#define CACHERR_D CE_D_MASK /* data error, way1|way0 */
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#define CACHERR_TA CE_TA_MASK /* tag addr error, way1|way0 */
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#define CACHERR_TS CE_TS_MASK /* tag state error, way1|way0 */
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#define CACHERR_TM CE_TM_MASK /* PDcache: tag mode error, way1|way0 */
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#define CACHERR_SA CE_SA /* uncorrectable SysAd bus error */
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#define CACHERR_SC CE_SC /* uncorrectable SysCmd bus error */
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#define CACHERR_SR CE_SR /* uncorrectable SysResp bus error */
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#define CACHERR_PIDX_MASK CE_PINDX_MASK /* Pcache virtual blk index */
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#define CACHERR_SIDX_MASK CE_SINDX_MASK /* Scache physical blk index */
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/* target cache */
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#define CACH_PI 0x0 /* Primary instruction cache */
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#define CACH_PD 0x1 /* Primary data cache */
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#define CACH_S 0x3 /* Secondary cache */
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#define CACH_SD CACH_S /* Secondary Data cache */
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#define CACH_SI CACH_S /* Secondary Inst. cache */
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/* Cache operations */
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#define C_IINV 0x00 /* index invalidate (inst) */
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#define C_IWBINV 0x00 /* index writeback inval (d, 2ndary) */
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#define C_ILT 0x04 /* index load tag (all) */
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#define C_IST 0x08 /* index store tag (all) */
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#define C_HINV 0x10 /* hit invalidate (all) */
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#define C_HWBINV 0x14 /* hit writeback inv. (d, s) */
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#define C_BARRIER 0x14 /* cache barrier (i only)*/
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#define C_ILD 0x18 /* Index load data */
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#define C_ISD 0x1c /* Index store data */
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#define C_HWB C_HWBINV /* hit writeback inv. (d, s) */
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#if defined(_LANGUAGE_C)
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typedef struct cacheop_s {
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__uint64_t cop_address; /* address for operation */
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__uint32_t cop_operation; /* operation */
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__uint32_t cop_taghi; /* tag hi value */
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__uint32_t cop_taglo; /* tag lo value */
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__uint32_t cop_ecc; /* ecc register value */
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} cacheop_t;
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#endif
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/*
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* Diagnostic Register (CP0 register 22)
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*/
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#define DR_BP_MOD_SHF 16
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#define DR_BP_MOD_MASK (0x3 << DR_BP_MOD_SHF)
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#define DR_BP_2BITS_COUNTER (0x0 << DR_BP_MOD_SHF)
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#define DR_BP_NONE_TAKEN (0x1 << DR_BP_MOD_SHF)
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#define DR_BP_ALL_TAKEN (0x2 << DR_BP_MOD_SHF)
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#define DR_BP_BACK_TAKEN (0x3 << DR_BP_MOD_SHF)
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#if defined(_LANGUAGE_ASSEMBLY)
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/*
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* Macros: ICACHE, DCACHE, SCACHE
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* Purpose: Form "cache" assmebly language instructions
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* Paramters: op - Operation from cache operations above.
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* va/pa - virtual/physical address, in the form "offset(reg)"
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*/
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#define ICACHE(op, va) cache op+CACH_PI, va
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#define DCACHE(op, va) cache op+CACH_PD, va
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#define SCACHE(op, pa) cache op+CACH_S, pa
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/*
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* Macro: CACHE_BARRIER
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* Purpose: Form cache barrier assembler instruction
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* Parameters: none
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*/
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#define CACHE_BARRIER cache CACH_BARRIER,0(zero)
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#endif /* defined(_LANGUAGE_ASSEMBLEY) */
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/*
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* IP25 ECC frame has the following layout:
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*
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* +--------------------------------------------------+
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* | |
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* | CACHE_STACK_SIZE - per CPU stack |
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* | |
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* +--------------------------------------------------+
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* | ECCF - ecc handler extended frame |
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* +--------------------------------------------------+
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* | EFRAME - standard EFRAME |
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* +--------------------------------------------------+
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*
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* Total size is: ECCF_SIZE
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*/
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#define ECCF_STACK_SIZE 4096 /* Includes stack */
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#define ECCF_TRACE_CNT 16 /* cache error regs to trace */
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#if defined(_LANGUAGE_C)
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typedef struct eccframe_s {
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__uint64_t eccf_errorEPC; /* Current error EPC */
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__uint64_t eccf_tag; /* Current TAG */
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__uint32_t eccf_cache_err; /* Current cache error register */
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__uint32_t eccf_taglo; /* Current taglo value */
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__uint32_t eccf_taghi; /* Current taghi value */
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unsigned short eccf_ecc; /* Current ECC value */
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unsigned char eccf_status; /* current status - see below */
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uint eccf_icount; /* icache error count */
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uint eccf_dcount; /* dcache error count */
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uint eccf_scount; /* scache error count */
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uint eccf_sicount; /* system interface count */
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struct {
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__uint32_t ecct_cer;
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__uint64_t ecct_tag; /* tag of affected line */
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__uint64_t ecct_errepc;
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#if EVEREST
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__uint64_t ecct_rtc; /* clock - time of exception */
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#endif
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} eccf_trace[ECCF_TRACE_CNT];
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uint eccf_trace_idx; /* NEXT index to log into */
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uint eccf_putbuf_idx;/* NEXT index to read from */
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} eccframe_t;
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#define ECCF_ADD(a,b) (((a) + (b)) % ECCF_TRACE_CNT)
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#endif
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#define ECCF_STATUS_NORMAL 0
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#define ECCF_STATUS_ACTIVE 1
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#define ECCF_STATUS_PANIC 2
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/*
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* R10000 Configuration Cycle - These define the SYSAD values used
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* during the reset cycle.
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*/
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#define R10000_KSEG0CA_SHFT 0
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#define R10000_KSEG0CA_MASK (7 << R10000_KSEG0CA_SHFT)
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#define R10000_KSEG0CA(_B) ((_B) << R10000_KSEG0CA_SHFT)
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#define R10000_DEVNUM_SHFT 3
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#define R10000_DEVNUM_MASK (0x3 << R10000_DEVNUM_SHFT)
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#define R10000_DEVNUM(_B) ((_B) << R10000_DEVNUM_SHFT)
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#define R10000_CRPT_SHFT 5
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#define R10000_CRPT_MASK (1<<R10000_CRPT_SHFT)
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#define R10000_CPRT(_B) ((_B)<<R10000_CRPT_SHFT)
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#define R10000_PER_SHFT 6
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#define R10000_PER_MASK (1 << R10000_PER_SHFT)
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#define R10000_PER(_B) ((_B) << R10000_PER_SHFT)
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#define R10000_PRM_SHFT 7
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#define R10000_PRM_MASK (3 << R10000_PRM_SHFT)
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#define R10000_PRM(_B) ((_B) << R10000_PRM_SHFT)
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#define R10000_SCD_SHFT 9
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#define R10000_SCD_MASK (0xf << R10000_SCD_SHFT)
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#define R10000_SCD(_B) ((_B) << R10000_SCD_SHFT)
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#define R10000_SCBS_SHFT 13
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#define R10000_SCBS_MASK (1<<R10000_SCBS_SHFT)
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#define R10000_SCBS(_B) (((_B)) << R10000_SCBS_SHFT)
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#define R10000_SCCE_SHFT 14
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#define R10000_SCCE_MASK (1 << R10000_SCCE_SHFT)
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#define R10000_SCCE(_B) ((_B) << R10000_SCCE_SHFT)
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#define R10000_ME_SHFT 15
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#define R10000_ME_MASK (1 << R10000_ME_SHFT)
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#define R10000_ME(_B) ((_B) << R10000_ME_SHFT)
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#define R10000_SCS_SHFT 16
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#define R10000_SCS_MASK (0x7 << R10000_SCS_SHFT)
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#define R10000_SCS(_B) ((_B) << R10000_SCS_SHFT)
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#define R10000_SCCD_SHFT 19
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#define R10000_SCCD_MASK (0x7 << R10000_SCCD_SHFT)
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#define R10000_SCCD(_B) ((_B) << R10000_SCCD_SHFT)
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#define R10000_SCCT_SHFT 25
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#define R10000_SCCT_MASK (0xf << R10000_SCCT_SHFT)
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#define R10000_SCCT(_B) ((_B) << R10000_SCCT_SHFT)
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#define R10000_ODSC_SHFT 26
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#define R10000_ODSC_MASK (1 << R10000_ODSC_SHFT)
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#define R10000_ODSC(_B) ((_B) << R10000_ODSC_SHFT)
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#define R10000_ODSYS_SHFT 30
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#define R10000_ODSYS_MASK (1 << R10000_ODSYS_SHFT)
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#define R10000_ODSYS(_B) ((_B) << R10000_ODSYS_SHFT)
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#define R10000_CTM_SHFT 31
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#define R10000_CTM_MASK (1 << R10000_CTM_SHFT)
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#define R10000_CTM(_B) ((_B) << R10000_CTM_SHFT)
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#endif /* __SYS_R10K_H__ */
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