257 lines
8.1 KiB
C
257 lines
8.1 KiB
C
/*
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* Moosehead internal fast ethernet interface
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*
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* Copyright 1995, Silicon Graphics, Inc. All rights reserved.
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*/
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#ifndef SYS_MACE_ETHER_H
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#define SYS_MACE_ETHER_H
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#define MACE_ETHER_ADDRESS 0xBF280000
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/* Ethernet interface registers */
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struct mac110 {
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__uint32_t __mcpd;
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__uint32_t mac_control; /* MAC mode setup */
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union me_isr {
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__uint64_t lsr;
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struct {
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__uint32_t __ispd;
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__uint32_t sr; /* Interrupt status */
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} s;
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} isr;
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#define interrupt_status isr.s.sr
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__uint32_t __dcpd;
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__uint32_t dma_control; /* DMA control */
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__uint32_t __trpd;
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__uint32_t timer; /* Timer */
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__uint32_t __tapd;
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__uint32_t transmit_alias; /* Transmit interrupt (WO) */
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__uint32_t __rapd;
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__uint32_t receive_alias; /* Receive interrupt (WO) */
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struct {
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__uint32_t _tpd;
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union me_tir_u {
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__uint32_t td;
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struct me_tir {
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__uint32_t rptr:16, /* ring buffer read pointer */
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wptr:16; /* ring buffer write pointer */
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} bd;
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} u;
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} tx_info;
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#define tx_ring_rptr tx_info.u.bd.rptr
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#define tx_ring_wptr tx_info.u.bd.wptr
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#define tx_ring_regs tx_info.u.td
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__uint64_t pad1;
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struct {
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__uint32_t _rpd1;
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union me_rir_u {
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__uint32_t rd;
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struct me_rir {
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__uint32_t _rpd2:8,
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wptr:8, /* MCL fifo write pointer */
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rptr:8, /* MCL fifo read pointer */
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depth:8; /* MCL fifo depth */
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} bd;
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} u;
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} rx_info;
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#define rx_fifo_rptr rx_info.u.bd.rptr
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#define rx_fifo_wptr rx_info.u.bd.wptr
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#define rx_fifo_depth rx_info.u.bd.depth
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#define rx_fifo_regs rx_info.u.rd
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__uint64_t pad2;
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__uint64_t pad3;
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union {
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__uint64_t sintr_request;
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__uint64_t last_transmit_vector;
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} irltv;
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__uint32_t __ppd1;
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__uint32_t phy_dataio; /* PHY data r/w */
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__uint32_t __ppd2;
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__uint32_t phy_address; /* PHY fadr & radr */
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__uint32_t __ppd3;
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__uint32_t phy_read_start; /* PHY read start */
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__uint32_t __ppd4;
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__uint32_t backoff; /* Backoff LFSR */
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/* 64-bit DP-RAM locations in MACE */
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__uint64_t msgqueue[4]; /* read-only diag */
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__uint64_t physaddr; /* Physical address */
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__uint64_t secphysaddr; /* Physical address #2 */
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__uint64_t mlaf; /* Multicast filter */
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__uint64_t tx_ring_base; /* Transmit ring base */
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__uint64_t tx1_cmd_hdr; /* read-only diag */
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__uint64_t tx1_cat_ptr1; /* read-only diag */
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__uint64_t tx1_cat_ptr2; /* read-only diag */
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__uint64_t tx1_cat_ptr3; /* read-only diag */
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__uint64_t tx2_cmd_hdr; /* read-only diag */
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__uint64_t tx2_cat_ptr1; /* read-only diag */
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__uint64_t tx2_cat_ptr2; /* read-only diag */
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__uint64_t tx2_cat_ptr3; /* read-only diag */
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/* 64-bit DP-RAM FIFO locations in MACE */
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__uint32_t __rpd;
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__uint32_t rx_fifo;
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__uint64_t reserved5[31];
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};
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/* Multicast Logical Address Filter Macros */
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#define LAF_TSTBIT(laf, bit) \
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((laf) & (1LL << ((bit) & 0x3F)))
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#define LAF_SETBIT(laf, bit) \
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((laf) |= (1LL << ((bit) & 0x3F)))
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#define LAF_CLRBIT(laf, bit) \
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((laf) &= ~(1LL << ((bit) & 0x3F)))
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/* MAC Control Register */
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#define MAC_RESET 0x0001
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#define MAC_FULL_DUPLEX 0x0002
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#define MAC_LOOPBACK 0x0004
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#define MAC_100MBIT 0x0008
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#define MAC_SIA 0x0010
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#define MAC_FILTER 0x0060
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#define MAC_PHYSICAL 0x0000
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#define MAC_NORMAL 0x0020
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#define MAC_ALL_MULTICAST 0x0040
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#define MAC_PROMISCUOUS 0x0060
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#define MAC_LINKF 0x0080
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#define MAC_IPG 0x1FFFF00
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#define MAC_IPGT_SHIFT 8
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#define MAC_IPGR1_SHIFT 15
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#define MAC_IPGR2_SHIFT 22
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#define MAC_DEFAULT_IPG 0x54A9500 /* 21, 21, 21 */
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#define MAC_REV_SHIFT 29
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/* Interrupt Status Register */
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#define INTR_TX_DMA_REQ 0x01
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#define INTR_TX_PKT_REQ 0x02
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#define INTR_TX_LINK_FAIL 0x04
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#define INTR_TX_MEMORY_ERROR 0x08
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#define INTR_TX_ABORTED 0x10
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#define ETHER_TX_ERRORS (INTR_TX_LINK_FAIL | \
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INTR_TX_MEMORY_ERROR | \
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INTR_TX_ABORTED)
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#define INTR_RX_DMA_REQ 0x20
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#define INTR_RX_MSGS_UNDERFLOW 0x40
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#define INTR_RX_FIFO_OVERFLOW 0x80
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#define ETHER_RX_ERRORS (INTR_RX_MSGS_UNDERFLOW | \
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INTR_RX_FIFO_OVERFLOW)
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/* DMA control register */
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#define DMA_TX_INT_EN 0x0001
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#define DMA_TX_DMA_EN 0x0002
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#define DMA_TX_RINGMSK 0x000c
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#define DMA_TX_8K 0x0000
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#define DMA_TX_16K 0x0004
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#define DMA_TX_32K 0x0008
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#define DMA_TX_64K 0x000c
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#define DMA_TX_RINGMSK_SHIFT 2
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#define DMA_RX_THRSHD 0x01f0
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#define DMA_RX_INT_EN 0x0200
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#define DMA_RX_RUNTS_EN 0x0400
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#define DMA_RX_GATHER_EN 0x0800
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#define DMA_RX_OFFSET 0x7000
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#define DMA_RX_OFFSET_SHIFT 12
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#define DMA_RX_DMA_EN 0x8000
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/* Phy MDIO interface busy flag */
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#define MDIO_BUSY 0x10000
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/* Statistics vector format */
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typedef __uint64_t statistics_vector_t;
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/* Receive message cluster FIFO control */
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#define ETHER_RX_DMA_ENABLE 0x8000
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#define ETHER_RX_DMA_OFFSET 0x7000
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#define ETHER_RX_OFFSET_SHIFT 12
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#define ETHER_RX_MERGE_ENABLE 0x0800
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#define ETHER_RX_RUNT_ENABLE 0x0400
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#define ETHER_RX_INTR_ENABLE 0x0200
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#define ETHER_RX_THRESHOLD 0x01F0
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#define ETHER_RX_THRESH_SHIFT 4
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/* Transmit message cluster FIFO control */
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#define ETHER_TX_RING_SIZE 0x000C
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#define ETHER_TX_DMA_ENABLE 0x0002
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#define ETHER_TX_INTR_ENABLE 0x0001
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/* Receive status vector */
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#define RX_VEC_LENGTH 0x00007FFF
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#define RX_VEC_CODE_VIOLATION 0x00010000
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#define RX_VEC_DRIBBLE_NIBBLE 0x00020000
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#define RX_VEC_CRC_ERROR 0x00040000
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#define RX_VEC_MULTICAST 0x00080000
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#define RX_VEC_BROADCAST 0x00100000
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#define RX_VEC_INVALID_PREAMBLE 0x00200000
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#define RX_VEC_LONG_EVENT 0x00400000
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#define RX_VEC_BAD_PACKET 0x00800000
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#define RX_VEC_CARRIER_EVENT 0x01000000
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#define RX_VEC_MULTICAST_MATCH 0x02000000
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#define RX_VEC_PHYSICAL_MATCH 0x04000000
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#define RX_VEC_RECEIVE_SEQNUM 0xF8000000
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#define RX_VEC_RECEIVE_SEQNUM_SHIFT 27
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#define RX_VEC_FINISHED 0x8000000000000000ll
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#define RX_PROMISCUOUS \
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(RX_VEC_BROADCAST|RX_VEC_MULTICAST_MATCH|RX_VEC_PHYSICAL_MATCH)
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#define RX_VEC_CKSUM_SHIFT 32
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/* Transmit command header */
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#define TX_CMD_LENGTH 0x00007FFF
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#define TX_CMD_OFFSET 0x007F0000
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#define TX_CMD_OFFSET_SHIFT 16
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#define TX_CMD_TERM_DMA 0x00800000
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#define TX_CMD_SENT_INT_EN 0x01000000
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#define TX_CMD_CONCAT_1 0x02000000
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#define TX_CMD_CONCAT_2 0x04000000
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#define TX_CMD_CONCAT_3 0x08000000
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#define TX_CMD_NUM_CATS 3
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/* Transmit status vector */
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#define TX_VEC_LENGTH 0x00007FFF
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#define TX_VEC_COLLISIONS 0x000F0000
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#define TX_VEC_COLLISION_SHIFT 16
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#define TX_VEC_LATE_COLLISION 0x00100000
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#define TX_VEC_CRC_ERROR 0x00200000
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#define TX_VEC_DEFERRED 0x00400000
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#define TX_VEC_COMPLETED_SUCCESSFULLY 0x00800000
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#define TX_VEC_ABORTED_TOO_LONG 0x01000000
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#define TX_VEC_ABORTED_UNDERRUN 0x02000000
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#define TX_VEC_DROPPED_COLLISIONS 0x04000000
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#define TX_VEC_CANCELED_DEFERRAL 0x08000000
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#define TX_VEC_DROPPED_LATE_COLLISION 0x10000000
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#define TX_VEC_FINISHED 0x8000000000000000ll
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/* PHY defines */
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#define PHY_QS6612X 0x0181440 /* Quality TX */
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#define PHY_ICS1889 0x0015F41 /* ICS FX */
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#define PHY_ICS1890 0x0015F42 /* ICS TX */
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#define PHY_DP83840 0x20005C0 /* National TX */
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#define PHY_PCTL_RESET 0x8000 /* RESET */
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#define PHY_PCTL_LOOPBACK 0x4000 /* Loopback */
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#define PHY_PCTL_RATE 0x2000 /* 100Mbits */
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#define PHY_PCTL_AN_ENABLE 0x1000 /* AN enable */
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#define PHY_PCTL_POWERDOWN 0x0800 /* Powerdown PHY */
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#define PHY_PCTL_ISOLATE 0x0400 /* MII isolate */
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#define PHY_PCTL_RESTART_AN 0x0200 /* Restart AN */
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#define PHY_PCTL_DUPLEX 0x0100 /* Full duplex */
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#define PHY_PCTL_COLL_TEST 0x0080 /* Full duplex */
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#define PHY_PMSR_ANC 0x0020 /* PHY (1:5) */
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#define PHY_PMSR_FAULT 0x0010 /* PHY (1:6) */
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#define PHY_PMSR_ANA 0x0008 /* PHY (1:3) */
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#define PHY_PMSR_LINK 0x0004 /* PHY (1:2) */
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#define PHY_PMSR_JABBER 0x0002 /* PHY (1:1) */
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#define PHY_PMSR_ECAP 0x0001 /* PHY (1:0) */
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#define PHY_PLPA_TAF4 0x0200 /* PHY (5:9) */
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#define PHY_PLPA_TAF3 0x0100 /* PHY (5:8) */
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#define PHY_PLPA_TAF2 0x0080 /* PHY (5:7) */
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#define PHY_PLPA_TAF1 0x0040 /* PHY (5:6) */
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#define PHY_PLPA_TAF0 0x0020 /* PHY (5:5) */
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/* PHY errata structure */
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struct phyerrata {
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__uint32_t type;
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unsigned short rev, reg, mask, val;
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};
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#endif
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