1173 lines
37 KiB
C
1173 lines
37 KiB
C
/* Allocate registers within a basic block, for GNU compiler.
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Copyright (C) 1987, 1988 Free Software Foundation, Inc.
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This file is part of GNU CC.
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GNU CC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 1, or (at your option)
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any later version.
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GNU CC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GNU CC; see the file COPYING. If not, write to
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the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* Allocation of hard register numbers to pseudo registers is done in
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two passes. In this pass we consider only regs that are born and
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die once within one basic block. We do this one basic block at a
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time. Then the next pass allocates the registers that remain.
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Two passes are used because this pass uses methods that work only
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on linear code, but that do a better job than the general methods
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used in global_alloc, and more quickly too.
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The assignments made are recorded in the vector reg_renumber
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whose space is allocated here. The rtl code itself is not altered.
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We assign each instruction in the basic block a number
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which is its order from the beginning of the block.
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Then we can represent the lifetime of a pseudo register with
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a pair of numbers, and check for conflicts easily.
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We can record the availability of hard registers with a
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HARD_REG_SET for each instruction. The HARD_REG_SET
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contains 0 or 1 for each hard reg.
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To avoid register shuffling, we tie registers together when one
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dies by being copied into another, or dies in an instruction that
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does arithmetic to produce another. The tied registers are
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allocated as one. Registers with different reg class preferences
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can never be tied unless the class preferred by one is a subclass
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of the one preferred by the other.
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Tying is represented with "quantity numbers".
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A non-tied register is given a new quantity number.
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Tied registers have the same quantity number.
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We have provision to exempt registers, even when they are contained
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within the block, that can be tied to others that are not contained in it.
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This is so that global_alloc could process them both and tie them then.
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But this is currently disabled since tying in global_alloc is not
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yet implemented. */
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#include <stdio.h>
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#include "config.h"
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#include "rtl.h"
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#include "flags.h"
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#include "basic-block.h"
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#include "regs.h"
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#include "hard-reg-set.h"
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#include "insn-config.h"
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#include "recog.h"
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/* What about hardware registers used and set within same insn?
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Will that ever happen for a non-fixed register?
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Our lifetime-tracking for hardware registers would lose.
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[This caution is an old comment that may be obsolete;
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I think there is no longer a problem, but I'm not sure.] */
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/* Next quantity number available for allocation. */
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static int next_qty;
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/* In all the following vectors indexed by quantity number,
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only elements at indices >= FIRST_PSEUDO_REGISTER are actually used. */
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/* Element Q is the hard reg number chosen for quantity Q,
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or -1 if none was found. */
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static short *qty_phys_reg;
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/* Element Q is the hard reg number suggested for quantity Q,
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or -1 if no specific suggestion. */
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static short *qty_phys_sugg;
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/* Element Q is the number of refs to quantity Q. */
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static short *qty_n_refs;
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/* Element Q is a reg class contained in (smaller than) the
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preferred classes of all the pseudo regs that are tied in quantity Q.
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This is the preferred class for allocating that quantity. */
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static enum reg_class *qty_min_class;
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/* Insn number (counting from head of basic block)
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where quantity Q was born. -1 if birth has not been recorded. */
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static int *qty_birth;
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/* Insn number (counting from head of basic block)
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where quantity Q died. Due to the way tying is done,
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and the fact that we consider in this pass only regs that die but once,
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a quantity can die only once. Each quantity's life span
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is a set of consecutive insns. -1 if death has not been recorded. */
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static int *qty_death;
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/* Number of words needed to hold the data in quantity Q.
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This depends on its machine mode. It is used for these purposes:
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1. If it is 0, the qty is not really in use and is not allocated.
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2. It is used in computing the relative importances of qtys,
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which determines the order in which we look for regs for them.
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3. It is used in rules that prevent tying several registers of
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different sizes in a way that is geometrically impossible
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(see combine_regs). */
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static int *qty_size;
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/* This holds the mode of the registers that are tied to qty Q,
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or VOIDmode if registers with differing modes are tied together. */
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static enum machine_mode *qty_mode;
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/* Number of times a reg tied to qty Q lives across a CALL_INSN. */
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static int *qty_n_calls_crossed;
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/* Nonzero means don't allocate qty Q if we can't get its preferred class. */
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static char *qty_preferred_or_nothing;
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/* reg_qty[N] (where N is a pseudo reg number)
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is the qty number of that reg (which is >= FIRST_PSEUDO_REGISTER),
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or -1 if (REG N) is not local to the current basic block,
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or -2 if not known yet.
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If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is -1. */
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static int *reg_qty;
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/* The offset (in words) of register N within its quantity.
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This can be nonzero if register N is SImode, and has been tied
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to a subreg of a DImode register. */
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static int *reg_offset;
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/* Vector of substitutions of register numbers,
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used to map pseudo regs into hardware regs.
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This is set up as a result of register allocation.
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Element N is the hard reg assigned to pseudo reg N,
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or is -1 if no hard reg was assigned.
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If N is a hard reg number, element N is N. */
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short *reg_renumber;
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/* Set of hard registers live at the current point in the scan
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of the instructions in a basic block. */
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static HARD_REG_SET regs_live;
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/* Indexed by insn-number-within-basic-block,
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a set or hard registers live *after* that insn. */
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static HARD_REG_SET *regs_live_at;
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/* Nonzero if a CALL_INSN has been scanned
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but we have not yet seen a reference to the value returned. */
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static int call_seen;
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/* Communicate local vars `insn_number' and `insn'
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from `block_alloc' to `reg_is_set'. */
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static int this_insn_number;
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static rtx this_insn;
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static void block_alloc ();
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static int combine_regs ();
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static void wipe_dead_reg ();
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static int find_free_reg ();
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static void reg_is_born ();
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static void reg_is_set ();
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static void mark_life ();
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static void post_mark_life ();
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static int qty_compare ();
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static int qty_compare_1 ();
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static int reg_meets_class_p ();
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static int reg_class_subset_p ();
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static void update_qty_class ();
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/* Allocate a new quantity (new within current basic block)
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for register number REGNO which is born in insn number INSN_NUMBER
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within the block. MODE and SIZE are info on reg REGNO. */
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static void
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alloc_qty (regno, mode, size, insn_number)
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int regno;
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enum machine_mode mode;
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int size, insn_number;
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{
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register int qty = next_qty++;
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reg_qty[regno] = qty;
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reg_offset[regno] = 0;
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qty_size[qty] = size;
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qty_mode[qty] = mode;
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qty_birth[qty] = insn_number;
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qty_n_calls_crossed[qty] = reg_n_calls_crossed[regno];
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qty_min_class[qty] = reg_preferred_class (regno);
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qty_preferred_or_nothing[qty] = reg_preferred_or_nothing (regno);
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qty_n_refs[qty] = reg_n_refs[regno];
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}
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/* Main entry point of this file. */
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void
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local_alloc ()
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{
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register int b, i;
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/* Allocate vectors of temporary data.
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See the declarations of these variables, above,
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for what they mean. */
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qty_phys_reg = (short *) alloca (max_regno * sizeof (short));
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qty_phys_sugg = (short *) alloca (max_regno * sizeof (short));
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qty_birth = (int *) alloca (max_regno * sizeof (int));
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qty_death = (int *) alloca (max_regno * sizeof (int));
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qty_size = (int *) alloca (max_regno * sizeof (int));
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qty_mode = (enum machine_mode *) alloca (max_regno * sizeof (enum machine_mode));
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qty_n_calls_crossed = (int *) alloca (max_regno * sizeof (int));
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qty_min_class = (enum reg_class *) alloca (max_regno * sizeof (enum reg_class));
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qty_preferred_or_nothing = (char *) alloca (max_regno);
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qty_n_refs = (short *) alloca (max_regno * sizeof (short));
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reg_qty = (int *) alloca (max_regno * sizeof (int));
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reg_offset = (int *) alloca (max_regno * sizeof (int));
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reg_renumber = (short *) oballoc (max_regno * sizeof (short));
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for (i = 0; i < max_regno; i++)
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reg_renumber[i] = -1;
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/* This controls only how many elts of the `qty_...' vectors
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need to be zero for the first basic block. */
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next_qty = max_regno;
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/* Allocate each block's local registers, block by block. */
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for (b = 0; b < n_basic_blocks; b++)
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{
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for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
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{
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reg_qty[i] = -1;
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}
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for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
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{
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qty_phys_sugg[i] = -1;
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qty_birth[i] = -1;
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qty_death[i] = -1;
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/* Set reg_qty to -2 for pseudos in this block, -1 for others. */
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if (reg_basic_block[i] == b && reg_n_deaths[i] == 1)
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reg_qty[i] = -2;
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else
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reg_qty[i] = -1;
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}
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bzero (reg_offset, max_regno * sizeof (int));
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/* NEXT_QTY indicates which elements of the `qty_...'
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vectors might need to be initialized. Initialize those,
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with explicit loop if there are few, else with bzero. */
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if (next_qty < FIRST_PSEUDO_REGISTER + 6)
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{
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for (i = FIRST_PSEUDO_REGISTER; i < next_qty; i++)
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{
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qty_size[i] = 0;
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qty_mode[i] = VOIDmode;
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qty_min_class[i] = NO_REGS;
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qty_preferred_or_nothing[i] = 0;
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qty_n_calls_crossed[i] = 0;
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qty_n_refs[i] = 0;
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}
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}
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else
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{
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int clear_length = next_qty - FIRST_PSEUDO_REGISTER;
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#define CLEAR(vector) \
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bzero ((vector) + FIRST_PSEUDO_REGISTER, \
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(sizeof (*(vector))) * clear_length)
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CLEAR (qty_size);
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CLEAR (qty_mode);
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CLEAR (qty_min_class);
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CLEAR (qty_preferred_or_nothing);
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CLEAR (qty_n_calls_crossed);
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CLEAR (qty_n_refs);
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}
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next_qty = FIRST_PSEUDO_REGISTER;
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block_alloc (b);
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#ifdef USE_C_ALLOCA
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alloca (0);
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#endif
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}
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}
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/* Allocate hard regs to the pseudo regs used only within block number B.
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Only the pseudos that die but once can be handled. */
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static void
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block_alloc (b)
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int b;
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{
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register int i, q;
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register rtx insn;
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int insn_number = 0;
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int insn_count = 0;
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short *qty_order;
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call_seen = 0;
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/* Count the instructions in the basic block. */
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insn = basic_block_end[b];
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while (1)
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{
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if (GET_CODE (insn) != NOTE)
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insn_count++;
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if (insn == basic_block_head[b])
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break;
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insn = PREV_INSN (insn);
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}
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/* +1 to leave room for a post_mark_life at the last insn. */
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regs_live_at = (HARD_REG_SET *) alloca ((insn_count + 1)
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* sizeof (HARD_REG_SET));
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bzero (regs_live_at, (insn_count + 1) * sizeof (HARD_REG_SET));
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/* Initialize table of hardware registers currently live. */
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#ifdef HARD_REG_SET
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regs_live = *basic_block_live_at_start[b];
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#else
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COPY_HARD_REG_SET (regs_live, basic_block_live_at_start[b]);
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#endif
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/* This loop scans the instructions of the basic block
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and assigns quantities to registers.
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It computes which registers to tie. */
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insn = basic_block_head[b];
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while (1)
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{
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register rtx body = PATTERN (insn);
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if (GET_CODE (insn) != NOTE)
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insn_number++;
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if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
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|| GET_CODE (insn) == CALL_INSN)
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{
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register rtx link;
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register int win = 0;
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register rtx r0, r1;
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int combined_regno = -1;
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int insn_code_number = recog_memoized (insn);
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int commutative = 0;
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/* Set COMMUTATIVE if operands 1 and 2 are commutative. */
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if (insn_code_number >= 0
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&& insn_n_operands[insn_code_number] > 2
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&& insn_operand_constraint[insn_code_number][1][0] == '%')
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commutative = 1;
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/* Is this insn suitable for tying two registers?
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If so, try doing that.
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Suitable insns are (set reg0 reg1) and
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(set reg0 (arithop reg1 ...)).
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For a commutative operation, try (set reg0 (arithop ... reg1)).
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Subregs in place of regs are also ok.
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An insn with parallel sets is ok if the first set is suitable.
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If tying is done, WIN is set nonzero. */
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if (GET_CODE (body) == SET
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&& (r0 = SET_DEST (body),
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GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
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&& (r1 = SET_SRC (body),
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GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
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win = combine_regs (r1, r0, b, insn_number, insn);
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else if (GET_CODE (body) == SET)
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{
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r0 = SET_DEST (body);
|
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if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
|
||
{
|
||
if (GET_RTX_FORMAT (GET_CODE (SET_SRC (body)))[0] == 'e'
|
||
&& (r1 = XEXP (SET_SRC (body), 0),
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||
GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
|
||
win = combine_regs (r1, r0, b, insn_number, insn);
|
||
if (win == 0 && commutative
|
||
&& GET_RTX_FORMAT (GET_CODE (SET_SRC (body)))[1] == 'e'
|
||
&& (r1 = XEXP (SET_SRC (body), 1),
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GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
|
||
win = combine_regs (r1, r0, b, insn_number, insn);
|
||
}
|
||
}
|
||
else if (GET_CODE (body) == PARALLEL)
|
||
{
|
||
rtx set1 = XVECEXP (body, 0, 0);
|
||
if (GET_CODE (set1) == SET
|
||
&& (r0 = SET_DEST (set1),
|
||
GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
|
||
&& GET_RTX_FORMAT (GET_CODE (SET_SRC (set1)))[0] == 'e'
|
||
&& (r1 = XEXP (SET_SRC (set1), 0),
|
||
GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
|
||
win = combine_regs (r1, r0, b, insn_number, insn);
|
||
if (win == 0 && commutative && GET_CODE (set1) == SET
|
||
&& (r0 = SET_DEST (set1),
|
||
GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
|
||
&& GET_RTX_FORMAT (GET_CODE (SET_SRC (set1)))[1] == 'e'
|
||
&& (r1 = XEXP (SET_SRC (set1), 1),
|
||
GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
|
||
win = combine_regs (r1, r0, b, insn_number, insn);
|
||
}
|
||
|
||
/* If registers were just tied, set COMBINED_REGNO
|
||
to the number of the register used in this insn
|
||
that was tied to the register set in this insn.
|
||
This register's qty should not be "killed". */
|
||
|
||
if (win)
|
||
{
|
||
while (GET_CODE (r1) == SUBREG)
|
||
r1 = SUBREG_REG (r1);
|
||
combined_regno = REGNO (r1);
|
||
}
|
||
|
||
for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
|
||
{
|
||
/* Mark the death of everything that dies in this instruction,
|
||
except for anything that was just combined. */
|
||
if (XEXP (link, 0)
|
||
&& REG_NOTE_KIND (link) == REG_DEAD
|
||
&& combined_regno != REGNO (XEXP (link, 0)))
|
||
{
|
||
#if 0 /* The mechanism in reg_is_set that checks whether the qty dies here
|
||
ought to handle this case properly. */
|
||
if (combined_regno >= 0 &&
|
||
reg_qty[combined_regno] == reg_qty[REGNO (XEXP (link, 0))])
|
||
/* Here for the death of the quotient in a divmod insn:
|
||
something that was born and dead in this insn
|
||
but combined with something else that also dies here.
|
||
Mark the qty as dying one instruction later. */
|
||
wipe_dead_reg (XEXP (link, 0), insn_number,
|
||
insn_number + 1);
|
||
else
|
||
#endif
|
||
wipe_dead_reg (XEXP (link, 0), insn_number, insn_number);
|
||
}
|
||
/* Also, if this insn introduces a "constant" register,
|
||
that could just be replaced by the value it is given here
|
||
(which can legitimately be an immediate operand),
|
||
tell global-alloc not to allocate it
|
||
unless it is used at least twice more. */
|
||
|
||
else if (REG_NOTE_KIND (link) == REG_EQUIV
|
||
&& GET_CODE (SET_DEST (body)) == REG
|
||
&& general_operand (XEXP (link, 0), VOIDmode)
|
||
/* Don't inhibit allocation of a "constant" register
|
||
that we have already tied to something else! */
|
||
&& combined_regno < 0
|
||
/* Don't mess with things live during setjmp. */
|
||
&& reg_live_length[REGNO (SET_DEST (body))] >= 0)
|
||
{
|
||
i = REGNO (SET_DEST (body));
|
||
if (reg_n_sets[i] > 1)
|
||
{
|
||
/* Register is set in another place => not really constant.
|
||
cse or flow can cause this to happen.
|
||
Ok, forget we ever thought it was constant. */
|
||
GET_MODE (link) = VOIDmode;
|
||
}
|
||
else if (reg_n_refs[i] <= 2)
|
||
{
|
||
/* For a parameter copy, do let global-alloc
|
||
allocate it; otherwise we would be forced to
|
||
have a frame pointer. */
|
||
if (! frame_pointer_needed
|
||
&& GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
|
||
reg_live_length[i] = -2;
|
||
else
|
||
reg_live_length[i] = -1;
|
||
|
||
/* If value is not constant, we have a parameter
|
||
or a static chain pointer. Tell local-alloc
|
||
as well not to allocate it. */
|
||
if (! CONSTANT_P (SET_SRC (PATTERN (insn))))
|
||
{
|
||
reg_basic_block[i] = REG_BLOCK_GLOBAL;
|
||
reg_qty[i] = -1;
|
||
}
|
||
}
|
||
else
|
||
/* In any case, lower its priority for global-alloc. */
|
||
reg_live_length[i] *= 2;
|
||
}
|
||
}
|
||
|
||
/* Allocate qty numbers for all registers local to this block
|
||
that are born (set) in this instruction.
|
||
A pseudo that already has a qty is not changed. */
|
||
|
||
this_insn_number = insn_number;
|
||
this_insn = insn;
|
||
note_stores (PATTERN (insn), reg_is_set);
|
||
}
|
||
if (GET_CODE (insn) == CALL_INSN)
|
||
call_seen = 1;
|
||
if (insn == basic_block_end[b])
|
||
break;
|
||
/* We don't need this for the block's first instruction
|
||
since no regs we care about are live before that instruction.
|
||
Also we do not allocate space in regs_live_at for that instruction. */
|
||
IOR_HARD_REG_SET (regs_live_at[insn_number], regs_live);
|
||
insn = NEXT_INSN (insn);
|
||
}
|
||
|
||
/* Now every register that is local to this basic block
|
||
should have been given a quantity, or else -1 meaning ignore it.
|
||
Every quantity should have a known birth (verify this now).
|
||
|
||
If a qty's death has not been established, it indicates a dead store.
|
||
That is ok if the insn is not entirely dead.
|
||
So set the qty'd death to just after its birth. */
|
||
|
||
for (i = FIRST_PSEUDO_REGISTER; i < next_qty; i++)
|
||
{
|
||
if (qty_birth[i] == -1)
|
||
abort ();
|
||
if (qty_death[i] == -1)
|
||
qty_death[i] = qty_birth[i] + 1;
|
||
}
|
||
|
||
/* Now order the qtys so we assign them registers
|
||
in order of decreasing length of life. */
|
||
qty_order = (short *) alloca (next_qty * sizeof (short));
|
||
for (i = FIRST_PSEUDO_REGISTER; i < next_qty; i++)
|
||
qty_order[i] = i;
|
||
|
||
#define EXCHANGE(I1, I2) \
|
||
{ i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
|
||
|
||
if (next_qty == 2 + FIRST_PSEUDO_REGISTER)
|
||
{
|
||
if (qty_compare (FIRST_PSEUDO_REGISTER, FIRST_PSEUDO_REGISTER + 1) > 0)
|
||
EXCHANGE (FIRST_PSEUDO_REGISTER, FIRST_PSEUDO_REGISTER + 1);
|
||
}
|
||
else if (next_qty == 3 + FIRST_PSEUDO_REGISTER)
|
||
{
|
||
if (qty_compare (FIRST_PSEUDO_REGISTER, FIRST_PSEUDO_REGISTER + 1) > 0)
|
||
EXCHANGE (FIRST_PSEUDO_REGISTER, FIRST_PSEUDO_REGISTER + 1);
|
||
if (qty_compare (FIRST_PSEUDO_REGISTER + 1, FIRST_PSEUDO_REGISTER + 2) > 0)
|
||
EXCHANGE (FIRST_PSEUDO_REGISTER + 2, FIRST_PSEUDO_REGISTER + 1);
|
||
if (qty_compare (FIRST_PSEUDO_REGISTER, FIRST_PSEUDO_REGISTER + 1) > 0)
|
||
EXCHANGE (FIRST_PSEUDO_REGISTER, FIRST_PSEUDO_REGISTER + 1);
|
||
}
|
||
else if (next_qty > 3 + FIRST_PSEUDO_REGISTER)
|
||
qsort (qty_order + FIRST_PSEUDO_REGISTER,
|
||
next_qty - FIRST_PSEUDO_REGISTER, sizeof (short), qty_compare_1);
|
||
|
||
/* Now for each qty that is not a hardware register,
|
||
look for a hardware register to put it in.
|
||
First try the register class that is cheapest for this qty,
|
||
if there is more than one class. */
|
||
|
||
for (i = FIRST_PSEUDO_REGISTER; i < next_qty; i++)
|
||
{
|
||
q = qty_order[i];
|
||
if (qty_size[q] >= 0)
|
||
{
|
||
if (N_REG_CLASSES > 1)
|
||
{
|
||
qty_phys_reg[q] = find_free_reg (qty_min_class[q],
|
||
qty_mode[q], q, 0,
|
||
qty_birth[q], qty_death[q]);
|
||
if (qty_phys_reg[q] >= 0)
|
||
continue;
|
||
}
|
||
|
||
if (!qty_preferred_or_nothing[q])
|
||
qty_phys_reg[q] = find_free_reg (GENERAL_REGS,
|
||
qty_mode[q], q, 0,
|
||
qty_birth[q], qty_death[q]);
|
||
}
|
||
}
|
||
|
||
/* Now propagate the register assignments
|
||
to the pseudo regs belonging to the qtys. */
|
||
|
||
for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
|
||
if (reg_qty[i] >= 0 && qty_phys_reg[reg_qty[i]] >= 0)
|
||
{
|
||
reg_renumber[i] = qty_phys_reg[reg_qty[i]] + reg_offset[i];
|
||
}
|
||
}
|
||
|
||
/* Compare two quantities' priority for getting real registers.
|
||
We give quantities with hard-reg suggestions priority over all others.
|
||
We give longer-lived quantities higher priority
|
||
so that the shorter-lived ones will tend to be in the same places
|
||
which gives in general the maximum room for the regs to
|
||
be allocated by global-alloc.
|
||
Regs with more references are also preferred. */
|
||
|
||
static int
|
||
qty_compare (q1, q2)
|
||
int q1, q2;
|
||
{
|
||
register int tem = (qty_phys_sugg[q2] >= 0) - (qty_phys_sugg[q1] >= 0);
|
||
if (tem != 0) return tem;
|
||
return -((qty_n_refs[q1] + qty_death[q1] - qty_birth[q1]) * qty_size[q2]
|
||
- (qty_n_refs[q2] + qty_death[q2] - qty_birth[q2]) * qty_size[q1]);
|
||
}
|
||
|
||
static int
|
||
qty_compare_1 (q1, q2)
|
||
short *q1, *q2;
|
||
{
|
||
register int tem = (qty_phys_sugg[*q2] >= 0) - (qty_phys_sugg[*q1] >= 0);
|
||
if (tem != 0) return tem;
|
||
tem = -((qty_n_refs[*q1] + qty_death[*q1] - qty_birth[*q1]) * qty_size[*q2]
|
||
- (qty_n_refs[*q2] + qty_death[*q2] - qty_birth[*q2]) * qty_size[*q1]);
|
||
if (tem != 0) return tem;
|
||
/* If qtys are equally good, sort by qty number,
|
||
so that the results of qsort leave nothing to chance. */
|
||
return *q1 - *q2;
|
||
}
|
||
|
||
/* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
|
||
Returns 1 if have done so, or 0 if cannot.
|
||
|
||
Combining registers means marking them as having the same quantity
|
||
and adjusting the offsets within the quantity if either of
|
||
them is a SUBREG).
|
||
|
||
We don't actually combine a hard reg with a pseudo; instead
|
||
we just record the hard reg as the suggestion for the pseudo's quantity.
|
||
If we really combined them, we could lose if the pseudo lives
|
||
across an insn that clobbers the hard reg (eg, movstr).
|
||
|
||
There are elaborate checks for the validity of combining. */
|
||
|
||
|
||
static int
|
||
combine_regs (usedreg, setreg, b, insn_number, insn)
|
||
rtx usedreg, setreg;
|
||
int b;
|
||
int insn_number;
|
||
rtx insn;
|
||
{
|
||
register int ureg, sreg;
|
||
register int offset = 0;
|
||
int usize, ssize;
|
||
register int sqty;
|
||
|
||
/* Determine the numbers and sizes of registers being used. */
|
||
|
||
while (GET_CODE (usedreg) == SUBREG)
|
||
{
|
||
offset += SUBREG_WORD (usedreg);
|
||
usedreg = SUBREG_REG (usedreg);
|
||
}
|
||
if (GET_CODE (usedreg) != REG)
|
||
return 0;
|
||
ureg = REGNO (usedreg);
|
||
usize = REG_SIZE (usedreg);
|
||
|
||
while (GET_CODE (setreg) == SUBREG)
|
||
{
|
||
offset -= SUBREG_WORD (setreg);
|
||
setreg = SUBREG_REG (setreg);
|
||
}
|
||
if (GET_CODE (setreg) != REG)
|
||
return 0;
|
||
sreg = REGNO (setreg);
|
||
ssize = REG_SIZE (setreg);
|
||
|
||
/* Do not combine registers unless one fits within the other. */
|
||
if (offset > 0 && usize + offset > ssize)
|
||
return 0;
|
||
if (offset < 0 && usize + offset < ssize)
|
||
return 0;
|
||
/* Do not combine with a smaller already-assigned object
|
||
if that smaller object is already combined with something bigger
|
||
or if that smaller object is a hard reg.
|
||
In the latter case, we would implicitly be using consecutive
|
||
hard regs, and there is no code to keep track of that.
|
||
(This is overcautious; we could check that ssize actually
|
||
requires more hard regs at this spot.) */
|
||
if (ssize > usize && reg_qty[ureg] >= FIRST_PSEUDO_REGISTER
|
||
&& usize < qty_size[reg_qty[ureg]])
|
||
return 0;
|
||
|
||
/* Don't do anything with the non-allocatable registers.
|
||
Also, don't suggest a call-clobberable register
|
||
for something that must live across calls.
|
||
Also, don't suggest a hardware register for anything larger than it. */
|
||
if (ureg < FIRST_PSEUDO_REGISTER)
|
||
{
|
||
if (fixed_regs[ureg])
|
||
return 0;
|
||
if (reg_n_calls_crossed[sreg] != 0 && call_used_regs[ureg])
|
||
return 0;
|
||
if (usize < ssize)
|
||
return 0;
|
||
}
|
||
|
||
if (sreg < FIRST_PSEUDO_REGISTER)
|
||
{
|
||
if (fixed_regs[sreg])
|
||
return 0;
|
||
if (reg_n_calls_crossed[ureg] != 0 && call_used_regs[sreg])
|
||
return 0;
|
||
if (ssize < usize)
|
||
return 0;
|
||
}
|
||
|
||
/* Don't tie something to itself. In most cases it would make no
|
||
difference, but it would screw up if the reg being tied to itself
|
||
also dies in this insn. */
|
||
|
||
if (ureg == sreg)
|
||
return 0;
|
||
|
||
/* Don't try to connect two different hardware registers. */
|
||
|
||
if (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
|
||
return 0;
|
||
|
||
/* Don't connect two different machine modes if they have different
|
||
implications as to which registers may be used. */
|
||
|
||
if (!MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
|
||
return 0;
|
||
|
||
/* Now, if one of UREG and SREG is a hard reg and the other is
|
||
a pseudo, record the hard reg as the qty_phys_sugg for the pseudo
|
||
instead of tying them. */
|
||
/* Return "failure" so that the lifespan of UREG is terminated here;
|
||
that way the two lifespans will be disjoint and nothing will prevent
|
||
the pseudo reg from being given this hard reg. */
|
||
|
||
if (ureg < FIRST_PSEUDO_REGISTER)
|
||
{
|
||
if (reg_qty[sreg] == -2)
|
||
reg_is_born (setreg, insn_number);
|
||
if (reg_qty[ureg] == -2)
|
||
reg_is_born (usedreg, insn_number);
|
||
if (reg_qty[sreg] >= 0)
|
||
qty_phys_sugg[reg_qty[sreg]] = ureg;
|
||
return 0;
|
||
}
|
||
if (sreg < FIRST_PSEUDO_REGISTER)
|
||
{
|
||
if (reg_qty[sreg] == -2)
|
||
reg_is_born (setreg, insn_number);
|
||
if (reg_qty[ureg] == -2)
|
||
reg_is_born (usedreg, insn_number);
|
||
/* If UREG already has a suggested hard reg, don't override it,
|
||
since the most likely case is on a risc machine
|
||
when a pseudo gets a subroutine result and is then returned by
|
||
this function. In this case, the outgoing register window
|
||
is probably a better place to use. */
|
||
if (reg_qty[ureg] >= 0
|
||
&& (qty_phys_sugg[reg_qty[ureg]] < 0
|
||
/* If the old suggestion is no good, override it. */
|
||
|| (qty_n_calls_crossed[reg_qty[ureg]] != 0
|
||
&& call_used_regs[qty_phys_sugg[reg_qty[ureg]]])))
|
||
qty_phys_sugg[reg_qty[ureg]] = sreg;
|
||
return 0;
|
||
}
|
||
|
||
/* Do nothing if SREG is a pseudo that already has a quantity
|
||
or if it isn't local to this basic block or dies more than once. */
|
||
|
||
if (reg_qty[sreg] != -2)
|
||
return 0;
|
||
|
||
/* Do nothing if UREG isn't local to this block or dies more than once.
|
||
We do this because global_alloc has no idea of tying,
|
||
so there is no use noting those local pseudos that could
|
||
profitably be delayed till global_alloc and get tied to global ones. */
|
||
|
||
if (reg_qty[ureg] == -1)
|
||
return 0;
|
||
|
||
/* We don't already know about SREG, so tie it to UREG
|
||
if this is the last use of UREG, provided the classes they want
|
||
are compatible. */
|
||
|
||
if (find_regno_note (insn, REG_DEAD, ureg)
|
||
&& (reg_qty[ureg] >= FIRST_PSEUDO_REGISTER
|
||
? reg_meets_class_p (sreg, qty_min_class[reg_qty[ureg]])
|
||
: reg_meets_class_p (sreg, reg_preferred_class (ureg))))
|
||
{
|
||
if (reg_qty[ureg] == -2)
|
||
reg_is_born (usedreg, insn_number);
|
||
sqty = reg_qty[sreg] = reg_qty[ureg];
|
||
if (sqty < FIRST_PSEUDO_REGISTER) abort ();
|
||
/* If SREG's reg class is smaller, set qty_min_class[SQTY]. */
|
||
update_qty_class (sqty, sreg);
|
||
reg_offset[sreg] = reg_offset[ureg] + offset;
|
||
if (sqty >= 0)
|
||
{
|
||
qty_n_calls_crossed[sqty] += reg_n_calls_crossed[sreg];
|
||
qty_n_refs[sqty] += reg_n_refs[sreg];
|
||
if (! reg_preferred_or_nothing (sreg))
|
||
qty_preferred_or_nothing[sqty] = 0;
|
||
if (usize < ssize)
|
||
{
|
||
register int i;
|
||
for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
|
||
if (reg_qty[i] == sqty)
|
||
reg_offset[i] -= offset;
|
||
qty_size[sqty] = ssize;
|
||
qty_mode[sqty] = GET_MODE (setreg);
|
||
}
|
||
}
|
||
}
|
||
else
|
||
return 0;
|
||
|
||
return 1;
|
||
}
|
||
|
||
/* Return 1 if the preferred class of REG allows it to be tied
|
||
to a quantity or register whose class is CLASS.
|
||
True if REG's reg class either contains or is contained in CLASS. */
|
||
|
||
static int
|
||
reg_meets_class_p (reg, class)
|
||
int reg;
|
||
enum reg_class class;
|
||
{
|
||
register enum reg_class rclass = reg_preferred_class (reg);
|
||
return (reg_class_subset_p (rclass, class)
|
||
|| reg_class_subset_p (class, rclass));
|
||
}
|
||
|
||
/* Return nonzero if R2's preferred class is the same as or contains
|
||
R1's preferred class. R1 and R2 are pseudo-register numbers. */
|
||
|
||
static int
|
||
reg_class_subset_p (c1, c2)
|
||
register enum reg_class c1;
|
||
register enum reg_class c2;
|
||
{
|
||
if (c1 == c2) return 1;
|
||
|
||
if (c2 == ALL_REGS)
|
||
win:
|
||
return 1;
|
||
GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
|
||
reg_class_contents[(int)c2],
|
||
win);
|
||
return 0;
|
||
}
|
||
|
||
/* Update the class of QTY assuming that REG is being tied to it. */
|
||
|
||
static void
|
||
update_qty_class (qty, reg)
|
||
int qty;
|
||
int reg;
|
||
{
|
||
enum reg_class rclass = reg_preferred_class (reg);
|
||
if (reg_class_subset_p (rclass, qty_min_class[qty]))
|
||
qty_min_class[qty] = rclass;
|
||
}
|
||
|
||
/* Handle something which alters the value of an rtx REG.
|
||
REG is whatever is set or clobbered. (CLOBBER_FLAG says which.)
|
||
If it is not really a register, we do nothing.
|
||
The file-global variables `this_insn' and `this_insn_number'
|
||
carry info from `block_alloc'. */
|
||
|
||
static void
|
||
reg_is_set (reg, setter)
|
||
rtx reg;
|
||
rtx setter;
|
||
{
|
||
register int regno;
|
||
int clobber_flag = GET_CODE (setter) == CLOBBER;
|
||
|
||
if (reg == 0 || GET_CODE (reg) != REG)
|
||
return;
|
||
|
||
regno = REGNO (reg);
|
||
|
||
if (regno < FIRST_PSEUDO_REGISTER)
|
||
{
|
||
/* A hard reg is set or clobbered.
|
||
Mark it as live at the moment immediately following this insn
|
||
so that no pseudo can live here at that time.
|
||
For a CLOBBER, mark it as live before this insn,
|
||
to make sure it is free during the entire insn. */
|
||
|
||
register int lim = regno + HARD_REGNO_NREGS (regno, GET_MODE (reg));
|
||
register int i;
|
||
for (i = regno; i < lim; i++)
|
||
{
|
||
SET_HARD_REG_BIT (regs_live_at[this_insn_number], i);
|
||
if (clobber_flag)
|
||
SET_HARD_REG_BIT (regs_live_at[this_insn_number - 1], i);
|
||
}
|
||
|
||
/* If the hard reg is given a useful value
|
||
and it does not die in this insn,
|
||
mark it as live indefinitely afterward. */
|
||
if (! clobber_flag
|
||
&& ! find_regno_note (this_insn, REG_DEAD, regno))
|
||
reg_is_born (reg, this_insn_number);
|
||
}
|
||
else if (! clobber_flag)
|
||
{
|
||
/* A pseudo-reg is set (not just clobbered). */
|
||
|
||
reg_is_born (reg, this_insn_number);
|
||
|
||
/* If a pseudo register dies in the same insn that sets it,
|
||
say it dies in the following insn instead,
|
||
because it will have to be live right after this insn. */
|
||
if (qty_death[reg_qty[regno]] == this_insn_number)
|
||
{
|
||
/* Calls to post_mark_life and mark_life deleted here.
|
||
They only know how to handle hard regs. */
|
||
qty_death[reg_qty[regno]]++;
|
||
}
|
||
}
|
||
else if (reg_qty[regno] >= 0 && qty_death[reg_qty[regno]] == this_insn_number
|
||
&& qty_birth[reg_qty[regno]] == this_insn_number)
|
||
{
|
||
/* A psuedo-reg is clobbered by this insn and was born and dies here.
|
||
This is a temporary required for this insn and so will
|
||
conflict with any other live registers at this point. We must
|
||
assume that this register is used before all the inputs of the
|
||
insn are dead. So this register must not conflict with any of them.
|
||
Mark it as born at the previous insn. */
|
||
qty_birth[reg_qty[regno]]--;
|
||
/* It should also conflict with this insn's outputs. */
|
||
qty_death[reg_qty[regno]]++;
|
||
}
|
||
}
|
||
|
||
/* Handle beginning of the life of register REG.
|
||
INSN_NUMBER is the insn at which this is happening. */
|
||
|
||
static void
|
||
reg_is_born (reg, insn_number)
|
||
rtx reg;
|
||
int insn_number;
|
||
{
|
||
register int regno = REGNO (reg);
|
||
|
||
if (regno < FIRST_PSEUDO_REGISTER)
|
||
mark_life (regno, GET_MODE (reg), 1);
|
||
else if (reg_qty[regno] == -2)
|
||
alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), insn_number);
|
||
}
|
||
|
||
/* Record the death in insn DEATH_INSN_NUMBER for the register REG. */
|
||
|
||
static void
|
||
wipe_dead_reg (reg, this_insn_number, death_insn_number)
|
||
register rtx reg;
|
||
int this_insn_number;
|
||
int death_insn_number;
|
||
{
|
||
register int regno = REGNO (reg);
|
||
|
||
if (regno < FIRST_PSEUDO_REGISTER)
|
||
{
|
||
mark_life (regno, GET_MODE (reg), 0);
|
||
if (this_insn_number != death_insn_number)
|
||
abort ();
|
||
#if 0 /* Should never get here */
|
||
post_mark_life (regno, GET_MODE (reg), 1,
|
||
this_insn_number, death_insn_number);
|
||
#endif
|
||
}
|
||
else
|
||
{
|
||
/* If a pseudo reg is referred to but was never set,
|
||
we will find here that its qty is -2.
|
||
Since these regs do not conflict with anything,
|
||
mark them as born and dead in the same place. */
|
||
if (reg_qty[regno] == -2)
|
||
alloc_qty (regno, GET_MODE (reg), REG_SIZE (reg), this_insn_number);
|
||
|
||
if (reg_qty[regno] >= 0)
|
||
qty_death[reg_qty[regno]] = death_insn_number;
|
||
}
|
||
}
|
||
|
||
/* Find a block of SIZE words of hard regs in reg_class CLASS
|
||
that can hold something of machine-mode MODE
|
||
(but actually we test only the first of the block for holding MODE)
|
||
and still free between insn BORN_INSN and insn DEAD_INSN,
|
||
and return the number of the first of them.
|
||
Return -1 if such a block cannot be found.
|
||
If QTY crosses calls, insist on a register preserved by calls,
|
||
unless ACCEPT_CALL_CLOBBERED is nonzero. */
|
||
|
||
static int
|
||
find_free_reg (class, mode, qty, accept_call_clobbered, born_insn, dead_insn)
|
||
enum reg_class class;
|
||
enum machine_mode mode;
|
||
int accept_call_clobbered;
|
||
int qty;
|
||
int born_insn, dead_insn;
|
||
{
|
||
register int i, ins;
|
||
#ifdef HARD_REG_SET
|
||
register /* Declare it register if it's a scalar. */
|
||
#endif
|
||
HARD_REG_SET used;
|
||
|
||
if (accept_call_clobbered)
|
||
COPY_HARD_REG_SET (used, call_fixed_reg_set);
|
||
else if (qty_n_calls_crossed[qty] == 0)
|
||
COPY_HARD_REG_SET (used, fixed_reg_set);
|
||
else
|
||
COPY_HARD_REG_SET (used, call_used_reg_set);
|
||
|
||
for (ins = born_insn; ins < dead_insn; ins++)
|
||
IOR_HARD_REG_SET (used, regs_live_at[ins]);
|
||
|
||
IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
|
||
/* Don't use the frame pointer reg in local-alloc even if
|
||
we may omit the frame pointer, because if we do that and then we
|
||
need a frame pointer, reload won't know how to move the pseudo
|
||
to another hard reg. It can move only regs made by global-alloc. */
|
||
SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
|
||
|
||
/* If quantity QTY has a suggested physical register,
|
||
try that one first. */
|
||
|
||
if (qty_phys_sugg[qty] >= 0)
|
||
{
|
||
i = qty_phys_sugg[qty];
|
||
if (! TEST_HARD_REG_BIT (used, i)
|
||
&& HARD_REGNO_MODE_OK (i, mode))
|
||
{
|
||
register int j;
|
||
register int size1 = HARD_REGNO_NREGS (i, mode);
|
||
for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, i + j); j++);
|
||
if (j == size1)
|
||
{
|
||
post_mark_life (i, mode, 1, born_insn, dead_insn);
|
||
return i;
|
||
}
|
||
}
|
||
}
|
||
|
||
/* If that doesn't find one, test each hard reg. */
|
||
|
||
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
|
||
{
|
||
#ifdef REG_ALLOC_ORDER
|
||
int regno = reg_alloc_order[i];
|
||
#else
|
||
int regno = i;
|
||
#endif
|
||
if (! TEST_HARD_REG_BIT (used, regno)
|
||
&& HARD_REGNO_MODE_OK (regno, mode))
|
||
{
|
||
register int j;
|
||
register int size1 = HARD_REGNO_NREGS (regno, mode);
|
||
for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
|
||
if (j == size1)
|
||
{
|
||
post_mark_life (regno, mode, 1, born_insn, dead_insn);
|
||
return regno;
|
||
}
|
||
#ifndef REG_ALLOC_ORDER
|
||
i += j; /* Skip starting points we know will lose */
|
||
#endif
|
||
}
|
||
}
|
||
|
||
/* If it would be profitable to allocate a call-clobbered register
|
||
and save and restore it around calls, do that. */
|
||
|
||
if (! accept_call_clobbered
|
||
&& flag_caller_saves
|
||
&& qty_n_calls_crossed[qty] != 0
|
||
&& CALLER_SAVE_PROFITABLE (qty_n_refs[qty], qty_n_calls_crossed[qty]))
|
||
{
|
||
i = find_free_reg (class, mode, qty, 1, born_insn, dead_insn);
|
||
if (i >= 0)
|
||
caller_save_needed = 1;
|
||
return i;
|
||
}
|
||
return -1;
|
||
}
|
||
|
||
static void
|
||
mark_life (regno, mode, life)
|
||
register int regno;
|
||
enum machine_mode mode;
|
||
int life;
|
||
{
|
||
register int j = HARD_REGNO_NREGS (regno, mode);
|
||
if (life)
|
||
while (--j >= 0)
|
||
SET_HARD_REG_BIT (regs_live, regno + j);
|
||
else
|
||
while (--j >= 0)
|
||
CLEAR_HARD_REG_BIT (regs_live, regno + j);
|
||
}
|
||
|
||
static void
|
||
post_mark_life (regno, mode, life, birth, death)
|
||
register int regno, life, birth;
|
||
enum machine_mode mode;
|
||
int death;
|
||
{
|
||
register int j = HARD_REGNO_NREGS (regno, mode);
|
||
#ifdef HARD_REG_SET
|
||
register /* Declare it register if it's a scalar. */
|
||
#endif
|
||
HARD_REG_SET this_reg;
|
||
|
||
CLEAR_HARD_REG_SET (this_reg);
|
||
while (--j >= 0)
|
||
SET_HARD_REG_BIT (this_reg, regno + j);
|
||
|
||
/* If a reg is born and dies in one insn,
|
||
consider it live after that insn. */
|
||
|
||
if (birth == death)
|
||
death++;
|
||
|
||
if (life)
|
||
while (birth < death)
|
||
{
|
||
IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
|
||
birth++;
|
||
}
|
||
else
|
||
while (birth < death)
|
||
{
|
||
AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
|
||
birth++;
|
||
}
|
||
}
|
||
|
||
void
|
||
dump_local_alloc (file)
|
||
FILE *file;
|
||
{
|
||
register int i;
|
||
for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
|
||
if (reg_renumber[i] != -1)
|
||
fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);
|
||
}
|