90 lines
3.6 KiB
Plaintext
90 lines
3.6 KiB
Plaintext
#
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# IP27 multi-processor product definitions.
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#
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# SN0 R10K with KONA
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#
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# Fundamental constants of the build tree (distinct from source tree).
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# They may be different for each product. Therefore if several products are
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# built from one source tree, that source tree should contain a commondefs
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# for each product.
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#
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SYSTEM = SVR4
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CPUBOARD= IP27
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COMPLEX = MP
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CPUARCH = R10000
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PRODDEFS=-DSN0
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GFXBOARD= KONA
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SUBGR = IP27
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KMODEOPT = -DDISCONTIG_PHYSMEM -DNUMA_BASE -DNUMA_PM \
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-DNUMA_TBORROW -DNUMA_MIGRATION -DNUMA_MIGR_CONTROL \
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-DNUMA_REPLICATION -DNUMA_REPL_CONTROL -DNUMA_SCHED \
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-DPTE_64BIT -DLARGE_CPU_COUNT -DHUB1_WAR \
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-DHUB1_II_TIMEOUT_WAR -DHUB1_INTR_WAR \
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-DBRIDGE_ERROR_INTR_WAR -DIP27_NIC_WAR -DHUB_POQ_PIO_WAR \
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-DMAPPED_KERNEL -DIOC3_INTR_WAR \
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-DHUB_ERR_STS_WAR -DHUB_MIGR_WAR \
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-DSN0_INTR_BROKEN -DFRU -DFORCE_ERRORS -DT5_WB_SURPRISE_WAR \
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-DREV1_BRIDGE_SUPPORTED -DMIDPLANE_NIC_WAR -DFAKE_ROUTER_SLOT_WAR
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SUBPRODUCT=H1
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LARGE_CPU_COUNT=1
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COMPILATION_MODEL=64
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IOC3_PIO_MODE=0
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include $(RELEASEDEFS)
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#
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# Workaround definitions
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#
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# -DHUB1_WAR - Change register definitions for HUB1. This will
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# be removed when we switch to Hub 2.
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# -DBRIDGE1_TIMEOUT_WAR - Adjust the arbitartion time to keep the
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# 1.0 bridge chip from corrupting data. Also disable
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# certain error interrupts.
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# -DHUB1_II_TIMEOUT_WAR - This is a nasty one. Periodically stop
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# _all_ I/O and reset the hub timeout value. See
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# hub_dmatimeout_kick().
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# -DHUB1_INTR_WAR - Send interrupts to the junk bus interrupt controller.
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# The II has a bug that makes non-cache-aligned writes
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# from the II corrupt DMA data.
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# -DBRIDGE_ERROR_INTR_WAR - We seem to get erroneous error interrupts
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# from the bridge. Disable BRIDGE_IMR_PCI_MST_TIMEOUT,
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# BRIDGE_ISR_RESP_XTLK_ERR, and BRIDGE_ISR_LLP_TX_RETRY
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# -DIP27_NIC_WAR - The numer in a can doesn't work on early IP27 boards.
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# -DHUB_POQ_PIO_WAR - 64-bit writes to HUB PI registers can cause
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# the PI to become confused and issue a bogus message.
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# do 32-bit writes knowing that T5 will provide all
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# of the bits and Hub will ignore the byte enables.
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#
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# -sw, 5/28/96
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#
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# IOC3_INTR_WAR: with the junk interrupt it is required that an interrupt
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# handler ensure that its interrupt line is deasserted before returning.
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# This is problematic in the case of the IOC3 because the status of the
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# interrupt line cannot be read atomically from the hardware, and
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# there are no common locks between the various IOC3 sub-devices. The
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# upshot is occasionally we return from the handler without deasserting
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# the interrupt line, and all subsequent interrupts are lost. The
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# simple workaround to this is to poll for the interrupt once per
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# second.
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# -tcl
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# HUB_MIGR_WAR: The hub logic to generate a migration interrupt based
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# on the difference of home and remote reference counters
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# is not right. Probably it will be fixed in rev2.1.
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# The workaround provides an alternative by not using
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# the migration difference threshold register.
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#
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# HUB_ERR_STS_WAR: If any write errors happen when the hub error
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# registers are clear, we start losing WRB and subsequently
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# hang the CPU. This WAR ensures that the error status registers
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# have a RRB error in them.
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#
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# T5_WB_SURPRISE_WAR: The T5 incorrectly acknowledges a cache line
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# invalidate under some circumstances. It later proceeds to
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# writeback the cache line, resulting in a protocol error. This
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# will be fixed in T5 2.6, but in the meanwhile this WAR
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# attempts to detect if we ran into this problem.
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# Later, we should be able to kill user processes refrerencing
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# the page and let the system not panic.
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#
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