580 lines
14 KiB
C
580 lines
14 KiB
C
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/** @defgroup rcc_file RCC peripheral API
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*
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* @ingroup peripheral_apis
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*
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* @brief <b>libopencm3 STM32F3xx Reset and Clock Control</b>
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*
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* @version 1.0.0
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*
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* @date 11 July 2013
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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* Modified by 2013 Fernando Cortes <fernando.corcam@gmail.com> (stm32f3)
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* Modified by 2013 Guillermo Rivera <memogrg@gmail.com> (stm32f3)
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/cm3/assert.h>
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/flash.h>
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#include <libopencm3/stm32/i2c.h>
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/* Set the default clock frequencies after reset. */
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uint32_t rcc_ahb_frequency = 8000000;
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uint32_t rcc_apb1_frequency = 8000000;
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uint32_t rcc_apb2_frequency = 8000000;
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const struct rcc_clock_scale rcc_hsi_configs[] = {
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{ /* 48MHz */
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.pllmul = RCC_CFGR_PLLMUL_MUL12,
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.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre1 = RCC_CFGR_PPRE_DIV2,
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.ppre2 = RCC_CFGR_PPRE_NODIV,
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.flash_waitstates = 1,
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.ahb_frequency = 48000000,
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.apb1_frequency = 24000000,
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.apb2_frequency = 48000000,
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},
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{ /* 64MHz */
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.pllmul = RCC_CFGR_PLLMUL_MUL16,
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.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre1 = RCC_CFGR_PPRE_DIV2,
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.ppre2 = RCC_CFGR_PPRE_NODIV,
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.flash_waitstates = 2,
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.ahb_frequency = 64000000,
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.apb1_frequency = 32000000,
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.apb2_frequency = 64000000,
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}
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};
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const struct rcc_clock_scale rcc_hse8mhz_configs[] = {
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{
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.pllsrc = RCC_CFGR_PLLSRC_HSE_PREDIV,
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.pllmul = RCC_CFGR_PLLMUL_MUL9,
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.plldiv = RCC_CFGR2_PREDIV_NODIV,
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.usbdiv1 = false,
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.flash_waitstates = 2,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre1 = RCC_CFGR_PPRE_DIV2,
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.ppre2 = RCC_CFGR_PPRE_NODIV,
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.ahb_frequency = 72e6,
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.apb1_frequency = 36e6,
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.apb2_frequency = 72e6,
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}
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};
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void rcc_osc_ready_int_clear(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CIR |= RCC_CIR_PLLRDYC;
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break;
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case RCC_HSE:
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RCC_CIR |= RCC_CIR_HSERDYC;
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break;
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case RCC_HSI:
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RCC_CIR |= RCC_CIR_HSIRDYC;
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break;
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case RCC_LSE:
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RCC_CIR |= RCC_CIR_LSERDYC;
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break;
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case RCC_LSI:
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RCC_CIR |= RCC_CIR_LSIRDYC;
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break;
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}
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}
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void rcc_osc_ready_int_enable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CIR |= RCC_CIR_PLLRDYIE;
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break;
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case RCC_HSE:
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RCC_CIR |= RCC_CIR_HSERDYIE;
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break;
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case RCC_HSI:
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RCC_CIR |= RCC_CIR_HSIRDYIE;
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break;
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case RCC_LSE:
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RCC_CIR |= RCC_CIR_LSERDYIE;
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break;
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case RCC_LSI:
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RCC_CIR |= RCC_CIR_LSIRDYIE;
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break;
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}
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}
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void rcc_osc_ready_int_disable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CIR &= ~RCC_CIR_PLLRDYIE;
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break;
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case RCC_HSE:
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RCC_CIR &= ~RCC_CIR_HSERDYIE;
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break;
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case RCC_HSI:
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RCC_CIR &= ~RCC_CIR_HSIRDYIE;
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break;
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case RCC_LSE:
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RCC_CIR &= ~RCC_CIR_LSERDYIE;
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break;
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case RCC_LSI:
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RCC_CIR &= ~RCC_CIR_LSIRDYIE;
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break;
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}
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}
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int rcc_osc_ready_int_flag(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
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break;
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case RCC_HSE:
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return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
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break;
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case RCC_HSI:
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return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
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break;
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case RCC_LSE:
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return ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
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break;
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case RCC_LSI:
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return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
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break;
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}
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cm3_assert_not_reached();
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}
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void rcc_css_int_clear(void)
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{
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RCC_CIR |= RCC_CIR_CSSC;
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}
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int rcc_css_int_flag(void)
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{
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return ((RCC_CIR & RCC_CIR_CSSF) != 0);
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}
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bool rcc_is_osc_ready(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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return RCC_CR & RCC_CR_PLLRDY;
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case RCC_HSE:
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return RCC_CR & RCC_CR_HSERDY;
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case RCC_HSI:
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return RCC_CR & RCC_CR_HSIRDY;
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case RCC_LSE:
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return RCC_BDCR & RCC_BDCR_LSERDY;
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case RCC_LSI:
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return RCC_CSR & RCC_CSR_LSIRDY;
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}
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return false;
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}
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void rcc_wait_for_osc_ready(enum rcc_osc osc)
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{
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while (!rcc_is_osc_ready(osc));
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}
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void rcc_wait_for_osc_not_ready(enum rcc_osc osc)
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{
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while (rcc_is_osc_ready(osc));
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}
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void rcc_wait_for_sysclk_status(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
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RCC_CFGR_SWS_PLL);
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break;
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case RCC_HSE:
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while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
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RCC_CFGR_SWS_HSE);
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break;
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case RCC_HSI:
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while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
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RCC_CFGR_SWS_HSI);
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break;
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default:
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/* Shouldn't be reached. */
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break;
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}
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}
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void rcc_osc_on(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CR |= RCC_CR_PLLON;
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break;
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case RCC_HSE:
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RCC_CR |= RCC_CR_HSEON;
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break;
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case RCC_HSI:
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RCC_CR |= RCC_CR_HSION;
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break;
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case RCC_LSE:
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RCC_BDCR |= RCC_BDCR_LSEON;
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break;
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case RCC_LSI:
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RCC_CSR |= RCC_CSR_LSION;
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break;
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}
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}
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void rcc_osc_off(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CR &= ~RCC_CR_PLLON;
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break;
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case RCC_HSE:
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RCC_CR &= ~RCC_CR_HSEON;
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break;
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case RCC_HSI:
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RCC_CR &= ~RCC_CR_HSION;
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break;
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case RCC_LSE:
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RCC_BDCR &= ~RCC_BDCR_LSEON;
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break;
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case RCC_LSI:
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RCC_CSR &= ~RCC_CSR_LSION;
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break;
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}
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}
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void rcc_css_enable(void)
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{
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RCC_CR |= RCC_CR_CSSON;
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}
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void rcc_css_disable(void)
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{
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RCC_CR &= ~RCC_CR_CSSON;
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}
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void rcc_set_sysclk_source(uint32_t clk)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 1) | (1 << 0));
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RCC_CFGR = (reg32 | clk);
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}
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void rcc_set_pll_source(uint32_t pllsrc)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~RCC_CFGR_PLLSRC;
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RCC_CFGR = (reg32 | (pllsrc << 16));
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}
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void rcc_set_ppre2(uint32_t ppre2)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
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RCC_CFGR = (reg32 | (ppre2 << RCC_CFGR_PPRE2_SHIFT));
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}
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void rcc_set_ppre1(uint32_t ppre1)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
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RCC_CFGR = (reg32 | (ppre1 << RCC_CFGR_PPRE1_SHIFT));
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}
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void rcc_set_hpre(uint32_t hpre)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_SHIFT);
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RCC_CFGR = (reg32 | (hpre << RCC_CFGR_HPRE_SHIFT));
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}
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/**
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* Set PLL Source pre-divider **CAUTION**.
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* On some F3 devices, prediv only applies to HSE source. On others,
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* this is _after_ source selection. See also f0.
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* @param[in] prediv division by prediv+1 @ref rcc_cfgr2_prediv
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*/
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void rcc_set_prediv(uint32_t prediv)
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{
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RCC_CFGR2 = (RCC_CFGR2 & ~RCC_CFGR2_PREDIV) | prediv;
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}
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void rcc_set_pll_multiplier(uint32_t pll)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_PLLMUL_MASK << RCC_CFGR_PLLMUL_SHIFT);
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RCC_CFGR = (reg32 | (pll << RCC_CFGR_PLLMUL_SHIFT));
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}
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uint32_t rcc_get_system_clock_source(void)
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{
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/* Return the clock source which is used as system clock. */
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return (RCC_CFGR & 0x000c) >> 2;
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}
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/**
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* Setup clocks to run from PLL.
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* The arguments provide the pll source, multipliers, dividers, all that's
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* needed to establish a system clock.
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* @param clock clock information structure
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*/
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void rcc_clock_setup_pll(const struct rcc_clock_scale *clock)
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{
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if (clock->pllsrc == RCC_CFGR_PLLSRC_HSE_PREDIV) {
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rcc_osc_on(RCC_HSE);
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rcc_wait_for_osc_ready(RCC_HSE);
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} else {
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rcc_osc_on(RCC_HSI);
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rcc_wait_for_osc_ready(RCC_HSI);
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||
|
|
}
|
||
|
|
rcc_osc_off(RCC_PLL);
|
||
|
|
rcc_usb_prescale_1_5();
|
||
|
|
if (clock->usbdiv1) {
|
||
|
|
rcc_usb_prescale_1();
|
||
|
|
}
|
||
|
|
rcc_wait_for_osc_not_ready(RCC_PLL);
|
||
|
|
rcc_set_pll_source(clock->pllsrc);
|
||
|
|
rcc_set_pll_multiplier(clock->pllmul);
|
||
|
|
rcc_set_prediv(clock->plldiv);
|
||
|
|
/* Enable PLL oscillator and wait for it to stabilize. */
|
||
|
|
rcc_osc_on(RCC_PLL);
|
||
|
|
rcc_wait_for_osc_ready(RCC_PLL);
|
||
|
|
|
||
|
|
/* Configure flash settings. */
|
||
|
|
flash_prefetch_enable();
|
||
|
|
flash_set_ws(clock->flash_waitstates);
|
||
|
|
|
||
|
|
rcc_set_hpre(clock->hpre);
|
||
|
|
rcc_set_ppre2(clock->ppre2);
|
||
|
|
rcc_set_ppre1(clock->ppre1);
|
||
|
|
/* Select PLL as SYSCLK source. */
|
||
|
|
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
|
||
|
|
/* Wait for PLL clock to be selected. */
|
||
|
|
rcc_wait_for_sysclk_status(RCC_PLL);
|
||
|
|
|
||
|
|
/* Set the peripheral clock frequencies used. */
|
||
|
|
rcc_ahb_frequency = clock->ahb_frequency;
|
||
|
|
rcc_apb1_frequency = clock->apb1_frequency;
|
||
|
|
rcc_apb2_frequency = clock->apb2_frequency;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
void __attribute__((deprecated)) rcc_clock_setup_hsi(const struct rcc_clock_scale *clock)
|
||
|
|
{
|
||
|
|
/* Enable internal high-speed oscillator. */
|
||
|
|
rcc_osc_on(RCC_HSI);
|
||
|
|
rcc_wait_for_osc_ready(RCC_HSI);
|
||
|
|
/* Select HSI as SYSCLK source. */
|
||
|
|
rcc_set_sysclk_source(RCC_CFGR_SW_HSI); /* XXX: se cayo */
|
||
|
|
rcc_wait_for_sysclk_status(RCC_HSI);
|
||
|
|
|
||
|
|
rcc_osc_off(RCC_PLL);
|
||
|
|
rcc_wait_for_osc_not_ready(RCC_PLL);
|
||
|
|
rcc_set_pll_source(clock->pllsrc);
|
||
|
|
rcc_set_pll_multiplier(clock->pllmul);
|
||
|
|
/* Enable PLL oscillator and wait for it to stabilize. */
|
||
|
|
rcc_osc_on(RCC_PLL);
|
||
|
|
rcc_wait_for_osc_ready(RCC_PLL);
|
||
|
|
/*
|
||
|
|
* Set prescalers for AHB, ADC, APB1, APB2.
|
||
|
|
* Do this before touching the PLL (TODO: why?).
|
||
|
|
*/
|
||
|
|
rcc_set_hpre(clock->hpre);
|
||
|
|
rcc_set_ppre2(clock->ppre2);
|
||
|
|
rcc_set_ppre1(clock->ppre1);
|
||
|
|
/* Configure flash settings. */
|
||
|
|
flash_set_ws(clock->flash_waitstates);
|
||
|
|
/* Select PLL as SYSCLK source. */
|
||
|
|
rcc_set_sysclk_source(RCC_CFGR_SW_PLL); /* XXX: se cayo */
|
||
|
|
/* Wait for PLL clock to be selected. */
|
||
|
|
rcc_wait_for_sysclk_status(RCC_PLL);
|
||
|
|
|
||
|
|
/* Set the peripheral clock frequencies used. */
|
||
|
|
rcc_ahb_frequency = clock->ahb_frequency;
|
||
|
|
rcc_apb1_frequency = clock->apb1_frequency;
|
||
|
|
rcc_apb2_frequency = clock->apb2_frequency;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
void rcc_backupdomain_reset(void)
|
||
|
|
{
|
||
|
|
/* Set the backup domain software reset. */
|
||
|
|
RCC_BDCR |= RCC_BDCR_BDRST;
|
||
|
|
|
||
|
|
/* Clear the backup domain software reset. */
|
||
|
|
RCC_BDCR &= ~RCC_BDCR_BDRST;
|
||
|
|
}
|
||
|
|
|
||
|
|
void rcc_set_i2c_clock_hsi(uint32_t i2c)
|
||
|
|
{
|
||
|
|
if (i2c == I2C1) {
|
||
|
|
RCC_CFGR3 &= ~RCC_CFGR3_I2C1SW;
|
||
|
|
}
|
||
|
|
if (i2c == I2C2) {
|
||
|
|
RCC_CFGR3 &= ~RCC_CFGR3_I2C2SW;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void rcc_set_i2c_clock_sysclk(uint32_t i2c)
|
||
|
|
{
|
||
|
|
if (i2c == I2C1) {
|
||
|
|
RCC_CFGR3 |= RCC_CFGR3_I2C1SW;
|
||
|
|
}
|
||
|
|
if (i2c == I2C2) {
|
||
|
|
RCC_CFGR3 |= RCC_CFGR3_I2C2SW;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
uint32_t rcc_get_i2c_clocks(void)
|
||
|
|
{
|
||
|
|
return RCC_CFGR3 & (RCC_CFGR3_I2C1SW | RCC_CFGR3_I2C2SW);
|
||
|
|
}
|
||
|
|
|
||
|
|
void rcc_usb_prescale_1_5(void)
|
||
|
|
{
|
||
|
|
RCC_CFGR &= ~RCC_CFGR_USBPRES;
|
||
|
|
}
|
||
|
|
|
||
|
|
void rcc_usb_prescale_1(void)
|
||
|
|
{
|
||
|
|
RCC_CFGR |= RCC_CFGR_USBPRES;
|
||
|
|
}
|
||
|
|
|
||
|
|
void rcc_adc_prescale(uint32_t prescale1, uint32_t prescale2)
|
||
|
|
{
|
||
|
|
uint32_t clear_mask = (RCC_CFGR2_ADCxPRES_MASK
|
||
|
|
<< RCC_CFGR2_ADC12PRES_SHIFT)
|
||
|
|
| (RCC_CFGR2_ADCxPRES_MASK
|
||
|
|
<< RCC_CFGR2_ADC34PRES_SHIFT);
|
||
|
|
uint32_t set = (prescale1 << RCC_CFGR2_ADC12PRES_SHIFT) |
|
||
|
|
(prescale2 << RCC_CFGR2_ADC34PRES_SHIFT);
|
||
|
|
RCC_CFGR2 &= ~(clear_mask);
|
||
|
|
RCC_CFGR2 |= (set);
|
||
|
|
}
|
||
|
|
|
||
|
|
static uint32_t rcc_get_usart_clksel_freq(uint32_t apb_clk, uint8_t shift) {
|
||
|
|
uint8_t clksel = (RCC_CFGR3 >> shift) & RCC_CFGR3_UARTxSW_MASK;
|
||
|
|
uint8_t hpre = (RCC_CFGR >> RCC_CFGR_HPRE_SHIFT) & RCC_CFGR_HPRE_MASK;
|
||
|
|
switch (clksel) {
|
||
|
|
case RCC_CFGR3_UART1SW_PCLK:
|
||
|
|
return apb_clk;
|
||
|
|
case RCC_CFGR3_UART1SW_SYSCLK:
|
||
|
|
return rcc_ahb_frequency * rcc_get_div_from_hpre(hpre);
|
||
|
|
case RCC_CFGR3_UART1SW_HSI:
|
||
|
|
return 8000000U;
|
||
|
|
}
|
||
|
|
cm3_assert_not_reached();
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief Get the peripheral clock speed for the USART at base specified.
|
||
|
|
* @param usart Base address of USART to get clock frequency for.
|
||
|
|
*/
|
||
|
|
uint32_t rcc_get_usart_clk_freq(uint32_t usart)
|
||
|
|
{
|
||
|
|
/* Handle values with selectable clocks. */
|
||
|
|
if (usart == USART1_BASE) {
|
||
|
|
return rcc_get_usart_clksel_freq(rcc_apb2_frequency, RCC_CFGR3_UART1SW_SHIFT);
|
||
|
|
} else if (usart == USART2_BASE) {
|
||
|
|
return rcc_get_usart_clksel_freq(rcc_apb1_frequency, RCC_CFGR3_UART2SW_SHIFT);
|
||
|
|
} else if (usart == USART3_BASE) {
|
||
|
|
return rcc_get_usart_clksel_freq(rcc_apb1_frequency, RCC_CFGR3_UART3SW_SHIFT);
|
||
|
|
} else if (usart == UART4_BASE) {
|
||
|
|
return rcc_get_usart_clksel_freq(rcc_apb1_frequency, RCC_CFGR3_UART4SW_SHIFT);
|
||
|
|
} else { /* UART5 */
|
||
|
|
return rcc_get_usart_clksel_freq(rcc_apb1_frequency, RCC_CFGR3_UART5SW_SHIFT);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief Get the peripheral clock speed for the Timer at base specified.
|
||
|
|
* @param timer Base address of TIM to get clock frequency for.
|
||
|
|
*/
|
||
|
|
uint32_t rcc_get_timer_clk_freq(uint32_t timer)
|
||
|
|
{
|
||
|
|
/* Handle APB1 timer clocks. */
|
||
|
|
if (timer >= TIM2_BASE && timer <= TIM7_BASE) {
|
||
|
|
uint8_t ppre1 = (RCC_CFGR >> RCC_CFGR_PPRE1_SHIFT) & RCC_CFGR_PPRE1_MASK;
|
||
|
|
return (ppre1 == RCC_CFGR_PPRE1_DIV_NONE) ? rcc_apb1_frequency
|
||
|
|
: 2 * rcc_apb1_frequency;
|
||
|
|
} else {
|
||
|
|
uint8_t ppre2 = (RCC_CFGR >> RCC_CFGR_PPRE2_SHIFT) & RCC_CFGR_PPRE2_MASK;
|
||
|
|
return (ppre2 == RCC_CFGR_PPRE2_DIV_NONE) ? rcc_apb2_frequency
|
||
|
|
: 2 * rcc_apb2_frequency;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief Get the peripheral clock speed for the I2C device at base specified.
|
||
|
|
* @param i2c Base address of I2C to get clock frequency for.
|
||
|
|
*/
|
||
|
|
uint32_t rcc_get_i2c_clk_freq(uint32_t i2c)
|
||
|
|
{
|
||
|
|
if (i2c == I2C1_BASE) {
|
||
|
|
if (RCC_CFGR3 & RCC_CFGR3_I2C1SW) {
|
||
|
|
uint8_t hpre = (RCC_CFGR >> RCC_CFGR_HPRE_SHIFT) & RCC_CFGR_HPRE_MASK;
|
||
|
|
return rcc_ahb_frequency * rcc_get_div_from_hpre(hpre);
|
||
|
|
} else {
|
||
|
|
return 8000000U;
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
return rcc_apb1_frequency;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief Get the peripheral clock speed for the SPI device at base specified.
|
||
|
|
* @param spi Base address of SPI device to get clock frequency for (e.g. SPI1_BASE).
|
||
|
|
*/
|
||
|
|
uint32_t rcc_get_spi_clk_freq(uint32_t spi) {
|
||
|
|
if (spi == SPI1_BASE || spi == SPI4_BASE) {
|
||
|
|
return rcc_apb2_frequency;
|
||
|
|
} else {
|
||
|
|
return rcc_apb1_frequency;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/**@}*/
|
||
|
|
|