git subrepo clone https://github.com/libopencm3/libopencm3
subrepo: subdir: "libopencm3" merged: "f5813a54" upstream: origin: "https://github.com/libopencm3/libopencm3" branch: "master" commit: "f5813a54" git-subrepo: version: "0.4.3" origin: "???" commit: "???"
This commit is contained in:
82
libopencm3/lib/stm32/f7/Makefile
Normal file
82
libopencm3/lib/stm32/f7/Makefile
Normal file
@@ -0,0 +1,82 @@
|
||||
##
|
||||
## This file is part of the libopencm3 project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
## Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
||||
##
|
||||
## This library is free software: you can redistribute it and/or modify
|
||||
## it under the terms of the GNU Lesser General Public License as published by
|
||||
## the Free Software Foundation, either version 3 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This library is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU Lesser General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU Lesser General Public License
|
||||
## along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
##
|
||||
|
||||
LIBNAME = libopencm3_stm32f7
|
||||
SRCLIBDIR ?= ../..
|
||||
|
||||
CC = $(PREFIX)gcc
|
||||
AR = $(PREFIX)ar
|
||||
|
||||
# STM32F7 only supports single precision FPU
|
||||
FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv5-sp-d16
|
||||
|
||||
TGT_CFLAGS = -Os \
|
||||
-Wall -Wextra -Wimplicit-function-declaration \
|
||||
-Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
|
||||
-Wundef -Wshadow \
|
||||
-I../../../include -fno-common \
|
||||
-mcpu=cortex-m7 -mthumb $(FP_FLAGS) \
|
||||
-Wstrict-prototypes \
|
||||
-ffunction-sections -fdata-sections -MD -DSTM32F7
|
||||
TGT_CFLAGS += $(DEBUG_FLAGS)
|
||||
TGT_CFLAGS += $(STANDARD_FLAGS)
|
||||
|
||||
ARFLAGS = rcs
|
||||
|
||||
OBJS += adc_common_v1.o adc_common_v1_multi.o adc_common_f47.o
|
||||
OBJS += can.o
|
||||
OBJS += crc_common_all.o crc_v2.o
|
||||
OBJS += dac_common_all.o dac_common_v1.o
|
||||
OBJS += dcmi_common_f47.o
|
||||
OBJS += desig_common_all.o desig.o
|
||||
OBJS += dma_common_f24.o
|
||||
OBJS += dma2d_common_f47.o
|
||||
OBJS += dsi_common_f47.o
|
||||
OBJS += exti_common_all.o
|
||||
OBJS += flash_common_all.o flash_common_f.o flash_common_f24.o flash.o
|
||||
OBJS += fmc_common_f47.o
|
||||
OBJS += gpio_common_all.o gpio_common_f0234.o
|
||||
OBJS += i2c_common_v2.o
|
||||
OBJS += iwdg_common_all.o
|
||||
OBJS += lptimer_common_all.o
|
||||
OBJS += ltdc_common_f47.o
|
||||
OBJS += pwr.o rcc.o
|
||||
OBJS += rcc_common_all.o
|
||||
OBJS += rng_common_v1.o
|
||||
OBJS += spi_common_all.o spi_common_v2.o
|
||||
OBJS += timer_common_all.o
|
||||
OBJS += usart_common_all.o usart_common_v2.o
|
||||
OBJS += quadspi_common_v1.o
|
||||
|
||||
# Ethernet
|
||||
OBJS += mac.o phy.o mac_stm32fxx7.o phy_ksz80x1.o
|
||||
|
||||
OBJS += usb.o usb_standard.o usb_control.o
|
||||
OBJS += usb_audio.o
|
||||
OBJS += usb_cdc.o
|
||||
OBJS += usb_hid.o
|
||||
OBJS += usb_midi.o
|
||||
OBJS += usb_msc.o
|
||||
OBJS += usb_dwc_common.o usb_f107.o usb_f207.o
|
||||
|
||||
VPATH += ../../usb:../:../../cm3:../common
|
||||
VPATH += ../../ethernet
|
||||
|
||||
include ../../Makefile.include
|
||||
72
libopencm3/lib/stm32/f7/desig.c
Normal file
72
libopencm3/lib/stm32/f7/desig.c
Normal file
@@ -0,0 +1,72 @@
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2019 Matthew Lai <m@matthewlai.ca>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/cm3/assert.h>
|
||||
#include <libopencm3/stm32/dbgmcu.h>
|
||||
#include <libopencm3/stm32/desig.h>
|
||||
|
||||
uint16_t desig_get_flash_size(void)
|
||||
{
|
||||
uint32_t device_id = DBGMCU_IDCODE & DBGMCU_IDCODE_DEV_ID_MASK;
|
||||
uint32_t* flash_size_base = 0;
|
||||
switch (device_id) {
|
||||
case 0x0449:
|
||||
flash_size_base = (uint32_t*) DESIG_FLASH_SIZE_BASE_449;
|
||||
break;
|
||||
case 0x0451:
|
||||
flash_size_base = (uint32_t*) DESIG_FLASH_SIZE_BASE_451;
|
||||
break;
|
||||
case 0x0452:
|
||||
flash_size_base = (uint32_t*) DESIG_FLASH_SIZE_BASE_452;
|
||||
break;
|
||||
}
|
||||
|
||||
if (!flash_size_base) {
|
||||
/* We don't know the address for this device. Hang here to help debugging. */
|
||||
cm3_assert_not_reached();
|
||||
}
|
||||
|
||||
return *flash_size_base;
|
||||
}
|
||||
|
||||
void desig_get_unique_id(uint32_t *result)
|
||||
{
|
||||
uint32_t device_id = DBGMCU_IDCODE & DBGMCU_IDCODE_DEV_ID_MASK;
|
||||
uint32_t* uid_base = 0;
|
||||
switch (device_id) {
|
||||
case 0x0449:
|
||||
uid_base = (uint32_t*) DESIG_UNIQUE_ID_BASE_449;
|
||||
break;
|
||||
case 0x0451:
|
||||
uid_base = (uint32_t*) DESIG_UNIQUE_ID_BASE_451;
|
||||
break;
|
||||
case 0x0452:
|
||||
uid_base = (uint32_t*) DESIG_UNIQUE_ID_BASE_452;
|
||||
break;
|
||||
}
|
||||
|
||||
if (!uid_base) {
|
||||
/* We don't know the address for this device. Hang here to help debugging. */
|
||||
cm3_assert_not_reached();
|
||||
}
|
||||
|
||||
result[0] = uid_base[2];
|
||||
result[1] = uid_base[1];
|
||||
result[2] = uid_base[0];
|
||||
}
|
||||
106
libopencm3/lib/stm32/f7/flash.c
Normal file
106
libopencm3/lib/stm32/f7/flash.c
Normal file
@@ -0,0 +1,106 @@
|
||||
/** @defgroup flash_file FLASH peripheral API
|
||||
*
|
||||
* @ingroup peripheral_apis
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2017 Matthew Lai @m@matthewlai.ca>
|
||||
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
|
||||
* Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/**@{*/
|
||||
|
||||
#include <libopencm3/stm32/flash.h>
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Issue Pipeline Stall
|
||||
|
||||
Issue a pipeline stall to make sure all write operations completed.
|
||||
|
||||
RM0385: After performing a data write operation and before polling the BSY bit
|
||||
to be cleared, the software can issue a DSB instruction to guarantee the
|
||||
completion of a previous data write operation.
|
||||
|
||||
*/
|
||||
|
||||
static inline void flash_pipeline_stall(void)
|
||||
{
|
||||
__asm__ volatile("dsb":::"memory");
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Wait until Last Operation has Ended
|
||||
|
||||
This loops indefinitely until an operation (write or erase) has completed by
|
||||
testing the busy flag.
|
||||
*/
|
||||
void flash_wait_for_last_operation(void)
|
||||
{
|
||||
flash_pipeline_stall();
|
||||
while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Clear the Erase Sequence Error Flag
|
||||
|
||||
This flag is set when an erase operation is performed with control register has
|
||||
not been correctly set.
|
||||
*/
|
||||
void flash_clear_erserr_flag(void)
|
||||
{
|
||||
FLASH_SR |= FLASH_SR_ERSERR;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Clear All Status Flags
|
||||
|
||||
Program error, end of operation, write protect error.
|
||||
*/
|
||||
|
||||
void flash_clear_status_flags(void)
|
||||
{
|
||||
flash_clear_erserr_flag();
|
||||
flash_clear_pgaerr_flag();
|
||||
flash_clear_wrperr_flag();
|
||||
flash_clear_pgperr_flag();
|
||||
flash_clear_eop_flag();
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Enable the ART Cache
|
||||
|
||||
*/
|
||||
|
||||
void flash_art_enable(void)
|
||||
{
|
||||
FLASH_ACR |= FLASH_ACR_ARTEN;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Reset the ART Cache
|
||||
|
||||
The ART cache must be disabled for this to have effect.
|
||||
*/
|
||||
|
||||
void flash_art_reset(void)
|
||||
{
|
||||
FLASH_ACR |= FLASH_ACR_ARTRST;
|
||||
}
|
||||
|
||||
/**@}*/
|
||||
70
libopencm3/lib/stm32/f7/pwr.c
Normal file
70
libopencm3/lib/stm32/f7/pwr.c
Normal file
@@ -0,0 +1,70 @@
|
||||
/** @defgroup pwr_file PWR peripheral API
|
||||
*
|
||||
* @ingroup peripheral_apis
|
||||
*
|
||||
* @brief <b>libopencm3 STM32F7xx Power Control</b>
|
||||
*
|
||||
* @version 1.0.0
|
||||
*
|
||||
* @author @htmlonly © @endhtmlonly 2011 Stephen Caudle <scaudle@doceme.com>
|
||||
* @author @htmlonly © @endhtmlonly 2017 Matthew Lai <m@matthewlai.ca>
|
||||
*
|
||||
* @date 12 March 2017
|
||||
*
|
||||
* This library supports the power control system for the
|
||||
* STM32F7 series of ARM Cortex Microcontrollers by ST Microelectronics.
|
||||
*
|
||||
* LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
|
||||
* Copyright (C) 2017 Matthew Lai <m@matthewlai.ca>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/stm32/pwr.h>
|
||||
|
||||
/**@{*/
|
||||
|
||||
void pwr_set_vos_scale(enum pwr_vos_scale scale)
|
||||
{
|
||||
PWR_CR1 &= ~PWR_CR1_VOS_MASK;
|
||||
|
||||
if (scale == PWR_SCALE1) {
|
||||
PWR_CR1 |= PWR_CR1_VOS_SCALE_1;
|
||||
} else if (scale == PWR_SCALE2) {
|
||||
PWR_CR1 |= PWR_CR1_VOS_SCALE_2;
|
||||
} else if (scale == PWR_SCALE3) {
|
||||
PWR_CR1 |= PWR_CR1_VOS_SCALE_3;
|
||||
}
|
||||
}
|
||||
|
||||
void pwr_enable_overdrive(void)
|
||||
{
|
||||
PWR_CR1 |= PWR_CR1_ODEN;
|
||||
while (!(PWR_CSR1 & PWR_CSR1_ODRDY));
|
||||
PWR_CR1 |= PWR_CR1_ODSWEN;
|
||||
while (!(PWR_CSR1 & PWR_CSR1_ODSWRDY));
|
||||
}
|
||||
|
||||
void pwr_disable_overdrive(void)
|
||||
{
|
||||
PWR_CR1 &= ~(PWR_CR1_ODEN | PWR_CR1_ODSWEN);
|
||||
while (!(PWR_CSR1 & PWR_CSR1_ODSWRDY));
|
||||
}
|
||||
|
||||
/**@}*/
|
||||
574
libopencm3/lib/stm32/f7/rcc.c
Normal file
574
libopencm3/lib/stm32/f7/rcc.c
Normal file
@@ -0,0 +1,574 @@
|
||||
/** @defgroup rcc_file RCC peripheral API
|
||||
*
|
||||
* @ingroup peripheral_apis
|
||||
* This library supports the Reset and Clock Control System in the STM32 series
|
||||
* of ARM Cortex Microcontrollers by ST Microelectronics.
|
||||
*
|
||||
* LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
|
||||
#include <libopencm3/cm3/assert.h>
|
||||
#include <libopencm3/stm32/rcc.h>
|
||||
#include <libopencm3/stm32/pwr.h>
|
||||
#include <libopencm3/stm32/flash.h>
|
||||
|
||||
/**@{*/
|
||||
|
||||
uint32_t rcc_ahb_frequency = 16000000;
|
||||
uint32_t rcc_apb1_frequency = 16000000;
|
||||
uint32_t rcc_apb2_frequency = 16000000;
|
||||
|
||||
// All PLL configurations without PLLM. PLLM should be set to the input clock
|
||||
// frequency in MHz.
|
||||
const struct rcc_clock_scale rcc_3v3[RCC_CLOCK_3V3_END] = {
|
||||
{ /* 216MHz */
|
||||
.plln = 432,
|
||||
.pllp = 2,
|
||||
.pllq = 9,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV2,
|
||||
.vos_scale = PWR_SCALE1,
|
||||
.overdrive = 1,
|
||||
.flash_waitstates = 7,
|
||||
.ahb_frequency = 216000000,
|
||||
.apb1_frequency = 54000000,
|
||||
.apb2_frequency = 108000000,
|
||||
},
|
||||
{ /* 168MHz */
|
||||
.plln = 336,
|
||||
.pllp = 2,
|
||||
.pllq = 7,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV2,
|
||||
.vos_scale = PWR_SCALE2,
|
||||
.overdrive = 1,
|
||||
.flash_waitstates = 5,
|
||||
.ahb_frequency = 168000000,
|
||||
.apb1_frequency = 42000000,
|
||||
.apb2_frequency = 84000000,
|
||||
},
|
||||
{ /* 120MHz */
|
||||
.plln = 240,
|
||||
.pllp = 2,
|
||||
.pllq = 5,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV2,
|
||||
.vos_scale = PWR_SCALE3,
|
||||
.overdrive = 0,
|
||||
.flash_waitstates = 3,
|
||||
.ahb_frequency = 120000000,
|
||||
.apb1_frequency = 30000000,
|
||||
.apb2_frequency = 60000000,
|
||||
},
|
||||
{ /* 72MHz */
|
||||
.plln = 144,
|
||||
.pllp = 2,
|
||||
.pllq = 3,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV2,
|
||||
.vos_scale = PWR_SCALE3,
|
||||
.overdrive = 0,
|
||||
.flash_waitstates = 2,
|
||||
.ahb_frequency = 72000000,
|
||||
.apb1_frequency = 18000000,
|
||||
.apb2_frequency = 36000000,
|
||||
},
|
||||
{ /* 48MHz */
|
||||
.plln = 192,
|
||||
.pllp = 4,
|
||||
.pllq = 4,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV2,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV2,
|
||||
.vos_scale = PWR_SCALE3,
|
||||
.overdrive = 0,
|
||||
.flash_waitstates = 1,
|
||||
.ahb_frequency = 48000000,
|
||||
.apb1_frequency = 24000000,
|
||||
.apb2_frequency = 24000000,
|
||||
},
|
||||
{ /* 24MHz */
|
||||
.plln = 192,
|
||||
.pllp = 8,
|
||||
.pllq = 4,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_NODIV,
|
||||
.ppre2 = RCC_CFGR_PPRE_NODIV,
|
||||
.vos_scale = PWR_SCALE3,
|
||||
.overdrive = 0,
|
||||
.flash_waitstates = 0,
|
||||
.ahb_frequency = 24000000,
|
||||
.apb1_frequency = 24000000,
|
||||
.apb2_frequency = 24000000,
|
||||
}
|
||||
};
|
||||
|
||||
void rcc_osc_ready_int_clear(enum rcc_osc osc)
|
||||
{
|
||||
switch (osc) {
|
||||
case RCC_PLL:
|
||||
RCC_CIR |= RCC_CIR_PLLRDYC;
|
||||
break;
|
||||
case RCC_HSE:
|
||||
RCC_CIR |= RCC_CIR_HSERDYC;
|
||||
break;
|
||||
case RCC_HSI:
|
||||
RCC_CIR |= RCC_CIR_HSIRDYC;
|
||||
break;
|
||||
case RCC_LSE:
|
||||
RCC_CIR |= RCC_CIR_LSERDYC;
|
||||
break;
|
||||
case RCC_LSI:
|
||||
RCC_CIR |= RCC_CIR_LSIRDYC;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rcc_osc_ready_int_enable(enum rcc_osc osc)
|
||||
{
|
||||
switch (osc) {
|
||||
case RCC_PLL:
|
||||
RCC_CIR |= RCC_CIR_PLLRDYIE;
|
||||
break;
|
||||
case RCC_HSE:
|
||||
RCC_CIR |= RCC_CIR_HSERDYIE;
|
||||
break;
|
||||
case RCC_HSI:
|
||||
RCC_CIR |= RCC_CIR_HSIRDYIE;
|
||||
break;
|
||||
case RCC_LSE:
|
||||
RCC_CIR |= RCC_CIR_LSERDYIE;
|
||||
break;
|
||||
case RCC_LSI:
|
||||
RCC_CIR |= RCC_CIR_LSIRDYIE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rcc_osc_ready_int_disable(enum rcc_osc osc)
|
||||
{
|
||||
switch (osc) {
|
||||
case RCC_PLL:
|
||||
RCC_CIR &= ~RCC_CIR_PLLRDYIE;
|
||||
break;
|
||||
case RCC_HSE:
|
||||
RCC_CIR &= ~RCC_CIR_HSERDYIE;
|
||||
break;
|
||||
case RCC_HSI:
|
||||
RCC_CIR &= ~RCC_CIR_HSIRDYIE;
|
||||
break;
|
||||
case RCC_LSE:
|
||||
RCC_CIR &= ~RCC_CIR_LSERDYIE;
|
||||
break;
|
||||
case RCC_LSI:
|
||||
RCC_CIR &= ~RCC_CIR_LSIRDYIE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
int rcc_osc_ready_int_flag(enum rcc_osc osc)
|
||||
{
|
||||
switch (osc) {
|
||||
case RCC_PLL:
|
||||
return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
|
||||
break;
|
||||
case RCC_HSE:
|
||||
return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
|
||||
break;
|
||||
case RCC_HSI:
|
||||
return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
|
||||
break;
|
||||
case RCC_LSE:
|
||||
return ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
|
||||
break;
|
||||
case RCC_LSI:
|
||||
return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
|
||||
break;
|
||||
}
|
||||
|
||||
cm3_assert_not_reached();
|
||||
}
|
||||
|
||||
void rcc_css_int_clear(void)
|
||||
{
|
||||
RCC_CIR |= RCC_CIR_CSSC;
|
||||
}
|
||||
|
||||
int rcc_css_int_flag(void)
|
||||
{
|
||||
return ((RCC_CIR & RCC_CIR_CSSF) != 0);
|
||||
}
|
||||
|
||||
void rcc_wait_for_osc_ready(enum rcc_osc osc)
|
||||
{
|
||||
switch (osc) {
|
||||
case RCC_PLL:
|
||||
while ((RCC_CR & RCC_CR_PLLRDY) == 0);
|
||||
break;
|
||||
case RCC_HSE:
|
||||
while ((RCC_CR & RCC_CR_HSERDY) == 0);
|
||||
break;
|
||||
case RCC_HSI:
|
||||
while ((RCC_CR & RCC_CR_HSIRDY) == 0);
|
||||
break;
|
||||
case RCC_LSE:
|
||||
while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0);
|
||||
break;
|
||||
case RCC_LSI:
|
||||
while ((RCC_CSR & RCC_CSR_LSIRDY) == 0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rcc_wait_for_sysclk_status(enum rcc_osc osc)
|
||||
{
|
||||
switch (osc) {
|
||||
case RCC_PLL:
|
||||
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL);
|
||||
break;
|
||||
case RCC_HSE:
|
||||
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE);
|
||||
break;
|
||||
case RCC_HSI:
|
||||
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI);
|
||||
break;
|
||||
default:
|
||||
/* Shouldn't be reached. */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rcc_osc_on(enum rcc_osc osc)
|
||||
{
|
||||
switch (osc) {
|
||||
case RCC_PLL:
|
||||
RCC_CR |= RCC_CR_PLLON;
|
||||
break;
|
||||
case RCC_HSE:
|
||||
RCC_CR |= RCC_CR_HSEON;
|
||||
break;
|
||||
case RCC_HSI:
|
||||
RCC_CR |= RCC_CR_HSION;
|
||||
break;
|
||||
case RCC_LSE:
|
||||
RCC_BDCR |= RCC_BDCR_LSEON;
|
||||
break;
|
||||
case RCC_LSI:
|
||||
RCC_CSR |= RCC_CSR_LSION;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rcc_osc_off(enum rcc_osc osc)
|
||||
{
|
||||
switch (osc) {
|
||||
case RCC_PLL:
|
||||
RCC_CR &= ~RCC_CR_PLLON;
|
||||
break;
|
||||
case RCC_HSE:
|
||||
RCC_CR &= ~RCC_CR_HSEON;
|
||||
break;
|
||||
case RCC_HSI:
|
||||
RCC_CR &= ~RCC_CR_HSION;
|
||||
break;
|
||||
case RCC_LSE:
|
||||
RCC_BDCR &= ~RCC_BDCR_LSEON;
|
||||
break;
|
||||
case RCC_LSI:
|
||||
RCC_CSR &= ~RCC_CSR_LSION;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rcc_css_enable(void)
|
||||
{
|
||||
RCC_CR |= RCC_CR_CSSON;
|
||||
}
|
||||
|
||||
void rcc_css_disable(void)
|
||||
{
|
||||
RCC_CR &= ~RCC_CR_CSSON;
|
||||
}
|
||||
|
||||
void rcc_set_sysclk_source(uint32_t clk)
|
||||
{
|
||||
uint32_t reg32;
|
||||
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~(RCC_CFGR_SW_MASK << RCC_CFGR_SW_SHIFT);
|
||||
RCC_CFGR = (reg32 | (clk << RCC_CFGR_SW_SHIFT));
|
||||
}
|
||||
|
||||
void rcc_set_pll_source(uint32_t pllsrc)
|
||||
{
|
||||
uint32_t reg32;
|
||||
|
||||
reg32 = RCC_PLLCFGR;
|
||||
reg32 &= ~(1 << 22);
|
||||
RCC_PLLCFGR = (reg32 | (pllsrc << 22));
|
||||
}
|
||||
|
||||
void rcc_set_ppre2(uint32_t ppre2)
|
||||
{
|
||||
uint32_t reg32;
|
||||
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
|
||||
RCC_CFGR = (reg32 | (ppre2 << RCC_CFGR_PPRE2_SHIFT));
|
||||
}
|
||||
|
||||
void rcc_set_ppre1(uint32_t ppre1)
|
||||
{
|
||||
uint32_t reg32;
|
||||
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
|
||||
RCC_CFGR = (reg32 | (ppre1 << RCC_CFGR_PPRE1_SHIFT));
|
||||
}
|
||||
|
||||
void rcc_set_hpre(uint32_t hpre)
|
||||
{
|
||||
uint32_t reg32;
|
||||
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_SHIFT);
|
||||
RCC_CFGR = (reg32 | (hpre << RCC_CFGR_HPRE_SHIFT));
|
||||
}
|
||||
|
||||
void rcc_set_rtcpre(uint32_t rtcpre)
|
||||
{
|
||||
uint32_t reg32;
|
||||
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~(RCC_CFGR_RTCPRE_MASK << RCC_CFGR_RTCPRE_SHIFT);
|
||||
RCC_CFGR = (reg32 | (rtcpre << RCC_CFGR_RTCPRE_SHIFT));
|
||||
}
|
||||
|
||||
void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp,
|
||||
uint32_t pllq)
|
||||
{
|
||||
RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
|
||||
(plln << RCC_PLLCFGR_PLLN_SHIFT) |
|
||||
(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
|
||||
(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
|
||||
}
|
||||
|
||||
void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp,
|
||||
uint32_t pllq)
|
||||
{
|
||||
RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
|
||||
(plln << RCC_PLLCFGR_PLLN_SHIFT) |
|
||||
(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
|
||||
RCC_PLLCFGR_PLLSRC |
|
||||
(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
|
||||
}
|
||||
|
||||
uint32_t rcc_system_clock_source(void)
|
||||
{
|
||||
/* Return the clock source which is used as system clock. */
|
||||
return (RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK;
|
||||
}
|
||||
|
||||
void rcc_clock_setup_hse(const struct rcc_clock_scale *clock, uint32_t hse_mhz)
|
||||
{
|
||||
uint8_t pllm = hse_mhz;
|
||||
|
||||
/* Enable internal high-speed oscillator. */
|
||||
rcc_osc_on(RCC_HSI);
|
||||
rcc_wait_for_osc_ready(RCC_HSI);
|
||||
|
||||
/* Select HSI as SYSCLK source. */
|
||||
rcc_set_sysclk_source(RCC_CFGR_SW_HSI);
|
||||
|
||||
/* Enable external high-speed oscillator. */
|
||||
rcc_osc_on(RCC_HSE);
|
||||
rcc_wait_for_osc_ready(RCC_HSE);
|
||||
|
||||
rcc_periph_clock_enable(RCC_PWR);
|
||||
pwr_set_vos_scale(clock->vos_scale);
|
||||
|
||||
if (clock->overdrive) {
|
||||
pwr_enable_overdrive();
|
||||
}
|
||||
|
||||
/*
|
||||
* Set prescalers for AHB, ADC, APB1, APB2.
|
||||
* Do this before touching the PLL (TODO: why?).
|
||||
*/
|
||||
rcc_set_hpre(clock->hpre);
|
||||
rcc_set_ppre1(clock->ppre1);
|
||||
rcc_set_ppre2(clock->ppre2);
|
||||
|
||||
/* Disable PLL oscillator before changing its configuration. */
|
||||
rcc_osc_off(RCC_PLL);
|
||||
|
||||
/* Configure the PLL oscillator. */
|
||||
rcc_set_main_pll_hse(pllm, clock->plln,
|
||||
clock->pllp, clock->pllq);
|
||||
|
||||
/* Enable PLL oscillator and wait for it to stabilize. */
|
||||
rcc_osc_on(RCC_PLL);
|
||||
rcc_wait_for_osc_ready(RCC_PLL);
|
||||
|
||||
/* Configure flash settings. */
|
||||
flash_set_ws(clock->flash_waitstates);
|
||||
flash_art_enable();
|
||||
flash_prefetch_enable();
|
||||
|
||||
/* Select PLL as SYSCLK source. */
|
||||
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
|
||||
|
||||
/* Wait for PLL clock to be selected. */
|
||||
rcc_wait_for_sysclk_status(RCC_PLL);
|
||||
|
||||
/* Set the clock frequencies used. */
|
||||
rcc_ahb_frequency = clock->ahb_frequency;
|
||||
rcc_apb1_frequency = clock->apb1_frequency;
|
||||
rcc_apb2_frequency = clock->apb2_frequency;
|
||||
|
||||
/* Disable internal high-speed oscillator. */
|
||||
rcc_osc_off(RCC_HSI);
|
||||
}
|
||||
|
||||
void rcc_clock_setup_hsi(const struct rcc_clock_scale *clock)
|
||||
{
|
||||
uint8_t pllm = 16;
|
||||
|
||||
/* Enable internal high-speed oscillator. */
|
||||
rcc_osc_on(RCC_HSI);
|
||||
rcc_wait_for_osc_ready(RCC_HSI);
|
||||
|
||||
/* Select HSI as SYSCLK source. */
|
||||
rcc_set_sysclk_source(RCC_CFGR_SW_HSI);
|
||||
|
||||
rcc_periph_clock_enable(RCC_PWR);
|
||||
pwr_set_vos_scale(clock->vos_scale);
|
||||
|
||||
if (clock->overdrive) {
|
||||
pwr_enable_overdrive();
|
||||
}
|
||||
|
||||
/*
|
||||
* Set prescalers for AHB, ADC, APB1, APB2.
|
||||
* Do this before touching the PLL (TODO: why?).
|
||||
*/
|
||||
rcc_set_hpre(clock->hpre);
|
||||
rcc_set_ppre1(clock->ppre1);
|
||||
rcc_set_ppre2(clock->ppre2);
|
||||
|
||||
rcc_set_main_pll_hsi(pllm, clock->plln,
|
||||
clock->pllp, clock->pllq);
|
||||
|
||||
/* Enable PLL oscillator and wait for it to stabilize. */
|
||||
rcc_osc_on(RCC_PLL);
|
||||
rcc_wait_for_osc_ready(RCC_PLL);
|
||||
|
||||
/* Configure flash settings. */
|
||||
flash_set_ws(clock->flash_waitstates);
|
||||
flash_art_enable();
|
||||
flash_prefetch_enable();
|
||||
|
||||
/* Select PLL as SYSCLK source. */
|
||||
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
|
||||
|
||||
/* Wait for PLL clock to be selected. */
|
||||
rcc_wait_for_sysclk_status(RCC_PLL);
|
||||
|
||||
/* Set the clock frequencies used. */
|
||||
rcc_ahb_frequency = clock->ahb_frequency;
|
||||
rcc_apb1_frequency = clock->apb1_frequency;
|
||||
rcc_apb2_frequency = clock->apb2_frequency;
|
||||
}
|
||||
|
||||
static uint32_t rcc_usart_i2c_clksel_freq(uint32_t apb_clk, uint8_t shift) {
|
||||
uint8_t clksel = (RCC_DCKCFGR2 >> shift) & RCC_DCKCFGR2_UART1SEL_MASK;
|
||||
uint8_t hpre = (RCC_CFGR >> RCC_CFGR_HPRE_SHIFT) & RCC_CFGR_HPRE_MASK;
|
||||
switch (clksel) {
|
||||
case RCC_DCKCFGR2_UARTxSEL_PCLK:
|
||||
return apb_clk;
|
||||
case RCC_DCKCFGR2_UARTxSEL_SYSCLK:
|
||||
return rcc_ahb_frequency * rcc_get_div_from_hpre(hpre);
|
||||
case RCC_DCKCFGR2_UARTxSEL_HSI:
|
||||
return 16000000U;
|
||||
default:
|
||||
cm3_assert_not_reached();
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Get the peripheral clock speed for the USART at base specified.
|
||||
* @param usart Base address of USART to get clock frequency for.
|
||||
*/
|
||||
uint32_t rcc_get_usart_clk_freq(uint32_t usart)
|
||||
{
|
||||
/* F7 is highly configurable, every USART can be configured in DCKCFGR2. */
|
||||
if (usart == USART1_BASE) {
|
||||
return rcc_usart_i2c_clksel_freq(rcc_apb2_frequency, RCC_DCKCFGR2_UART1SEL_SHIFT);
|
||||
} else if (usart == USART2_BASE) {
|
||||
return rcc_usart_i2c_clksel_freq(rcc_apb1_frequency, RCC_DCKCFGR2_UART2SEL_SHIFT);
|
||||
} else if (usart == USART3_BASE) {
|
||||
return rcc_usart_i2c_clksel_freq(rcc_apb1_frequency, RCC_DCKCFGR2_UART3SEL_SHIFT);
|
||||
} else if (usart == UART4_BASE) {
|
||||
return rcc_usart_i2c_clksel_freq(rcc_apb1_frequency, RCC_DCKCFGR2_UART4SEL_SHIFT);
|
||||
} else if (usart == UART5_BASE) {
|
||||
return rcc_usart_i2c_clksel_freq(rcc_apb1_frequency, RCC_DCKCFGR2_UART5SEL_SHIFT);
|
||||
} else if (usart == USART6_BASE) {
|
||||
return rcc_usart_i2c_clksel_freq(rcc_apb2_frequency, RCC_DCKCFGR2_USART6SEL_SHIFT);
|
||||
} else if (usart == UART7_BASE) {
|
||||
return rcc_usart_i2c_clksel_freq(rcc_apb1_frequency, RCC_DCKCFGR2_UART7SEL_SHIFT);
|
||||
} else { /* UART8 */
|
||||
return rcc_usart_i2c_clksel_freq(rcc_apb1_frequency, RCC_DCKCFGR2_UART8SEL_SHIFT);
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Get the peripheral clock speed for the Timer at base specified.
|
||||
* @param timer Base address of TIM to get clock frequency for.
|
||||
*/
|
||||
uint32_t rcc_get_timer_clk_freq(uint32_t timer)
|
||||
{
|
||||
/* Handle APB1 timer clocks. */
|
||||
if (timer >= TIM2_BASE && timer <= TIM14_BASE) {
|
||||
uint8_t ppre1 = (RCC_CFGR >> RCC_CFGR_PPRE1_SHIFT) & RCC_CFGR_PPRE1_MASK;
|
||||
return (ppre1 == RCC_CFGR_PPRE_DIV_NONE) ? rcc_apb1_frequency
|
||||
: 2 * rcc_apb1_frequency;
|
||||
} else {
|
||||
uint8_t ppre2 = (RCC_CFGR >> RCC_CFGR_PPRE2_SHIFT) & RCC_CFGR_PPRE2_MASK;
|
||||
return (ppre2 == RCC_CFGR_PPRE_DIV_NONE) ? rcc_apb2_frequency
|
||||
: 2 * rcc_apb2_frequency;
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Get the peripheral clock speed for the I2C device at base specified.
|
||||
* @param i2c Base address of I2C to get clock frequency for.
|
||||
*/
|
||||
uint32_t rcc_get_i2c_clk_freq(uint32_t i2c __attribute__((unused)))
|
||||
{
|
||||
if (i2c == I2C1_BASE) {
|
||||
return rcc_usart_i2c_clksel_freq(rcc_apb1_frequency, RCC_DCKCFGR2_I2C1SEL_SHIFT);
|
||||
} else if (i2c == I2C2_BASE) {
|
||||
return rcc_usart_i2c_clksel_freq(rcc_apb1_frequency, RCC_DCKCFGR2_I2C2SEL_SHIFT);
|
||||
} else if (i2c == I2C3_BASE) {
|
||||
return rcc_usart_i2c_clksel_freq(rcc_apb1_frequency, RCC_DCKCFGR2_I2C3SEL_SHIFT);
|
||||
} else { /* I2C4 */
|
||||
return rcc_usart_i2c_clksel_freq(rcc_apb1_frequency, RCC_DCKCFGR2_I2C4SEL_SHIFT);
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Get the peripheral clock speed for the SPI device at base specified.
|
||||
* @param spi Base address of SPI device to get clock frequency for (e.g. SPI1_BASE).
|
||||
*/
|
||||
uint32_t rcc_get_spi_clk_freq(uint32_t spi) {
|
||||
if (spi == SPI2_BASE || spi == SPI3_BASE) {
|
||||
return rcc_apb1_frequency;
|
||||
} else {
|
||||
return rcc_apb2_frequency;
|
||||
}
|
||||
}
|
||||
/**@}*/
|
||||
27
libopencm3/lib/stm32/f7/vector_chipset.c
Normal file
27
libopencm3/lib/stm32/f7/vector_chipset.c
Normal file
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
|
||||
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/cm3/scb.h>
|
||||
|
||||
static void pre_main(void)
|
||||
{
|
||||
/* Enable access to Floating-Point coprocessor. */
|
||||
SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11);
|
||||
}
|
||||
Reference in New Issue
Block a user