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  origin:   "https://github.com/libopencm3/libopencm3"
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  commit:   "f5813a54"
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Arti Zirk
2021-09-30 16:34:10 +03:00
parent 1a441e5806
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23
libopencm3/scripts/data/lpc43xx/README Normal file
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These files contain information derived from the LPC43xx user manual (UM10503).
They are intended to be used by scripts for the generation of header files and
functions.
Each line describes a field within a register. The comma separated values are:
register name (as found in include/lpc43xx/*.h),
bit position,
length in bits,
field name,
description/comment (may be empty if not specified in data sheet),
reset value (may be empty if not specified in data sheet),
access (may be empty if not specified in data sheet)
The access field may consist of any of the following codes:
r: read only
rw: read/write
rwc: read/write one to clear
rwo: read/write once
rws: read/write one to set
w: write only
ws: write one to set
Descriptions containing commas are quoted.

607
libopencm3/scripts/data/lpc43xx/adc.yaml Normal file
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!!omap
- ADC0_CR:
fields: !!omap
- SEL:
access: rw
description: Selects which of the ADCn_[7:0] inputs are to be sampled and
converted
lsb: 0
reset_value: '0'
width: 8
- CLKDIV:
access: rw
description: The ADC clock is divided by the CLKDIV value plus one to produce
the clock for the A/D converter
lsb: 8
reset_value: '0'
width: 8
- BURST:
access: rw
description: Controls Burst mode
lsb: 16
reset_value: '0'
width: 1
- CLKS:
access: rw
description: This field selects the number of clocks used for each conversion
in Burst mode and the number of bits of accuracy of the result in the LS
bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).
lsb: 17
reset_value: '0'
width: 3
- PDN:
access: rw
description: Power mode
lsb: 21
reset_value: '0'
width: 1
- START:
access: rw
description: Controls the start of an A/D conversion when the BURST bit is
0
lsb: 24
reset_value: '0'
width: 3
- EDGE:
access: rw
description: Controls rising or falling edge on the selected signal for the
start of a conversion
lsb: 27
reset_value: '0'
width: 1
- ADC1_CR:
fields: !!omap
- SEL:
access: rw
description: Selects which of the ADCn_[7:0] inputs are to be sampled and
converted
lsb: 0
reset_value: '0'
width: 8
- CLKDIV:
access: rw
description: The ADC clock is divided by the CLKDIV value plus one to produce
the clock for the A/D converter
lsb: 8
reset_value: '0'
width: 8
- BURST:
access: rw
description: Controls Burst mode
lsb: 16
reset_value: '0'
width: 1
- CLKS:
access: rw
description: This field selects the number of clocks used for each conversion
in Burst mode and the number of bits of accuracy of the result in the LS
bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).
lsb: 17
reset_value: '0'
width: 3
- PDN:
access: rw
description: Power mode
lsb: 21
reset_value: '0'
width: 1
- START:
access: rw
description: Controls the start of an A/D conversion when the BURST bit is
0
lsb: 24
reset_value: '0'
width: 3
- EDGE:
access: rw
description: Controls rising or falling edge on the selected signal for the
start of a conversion
lsb: 27
reset_value: '0'
width: 1
- ADC0_GDR:
fields: !!omap
- V_VREF:
access: r
description: When DONE is 1, this field contains a binary fraction representing
the voltage on the ADCn pin selected by the SEL field, divided by the reference
voltage on the VDDA pin
lsb: 6
reset_value: '0'
width: 10
- CHN:
access: r
description: These bits contain the channel from which the LS bits were converted
lsb: 24
reset_value: '0'
width: 3
- OVERRUN:
access: r
description: This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced the
result in the V_VREF bits
lsb: 30
reset_value: '0'
width: 1
- DONE:
access: r
description: This bit is set to 1 when an analog-to-digital conversion completes.
It is cleared when this register is read and when the AD0/1CR register is
written
lsb: 31
reset_value: '0'
width: 1
- ADC1_GDR:
fields: !!omap
- V_VREF:
access: r
description: When DONE is 1, this field contains a binary fraction representing
the voltage on the ADCn pin selected by the SEL field, divided by the reference
voltage on the VDDA pin
lsb: 6
reset_value: '0'
width: 10
- CHN:
access: r
description: These bits contain the channel from which the LS bits were converted
lsb: 24
reset_value: '0'
width: 3
- OVERRUN:
access: r
description: This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced the
result in the V_VREF bits
lsb: 30
reset_value: '0'
width: 1
- DONE:
access: r
description: This bit is set to 1 when an analog-to-digital conversion completes.
It is cleared when this register is read and when the AD0/1CR register is
written
lsb: 31
reset_value: '0'
width: 1
- ADC0_INTEN:
fields: !!omap
- ADINTEN:
access: rw
description: These bits allow control over which A/D channels generate interrupts
for conversion completion
lsb: 0
reset_value: '0'
width: 8
- ADGINTEN:
access: rw
description: When 1, enables the global DONE flag in ADDR to generate an interrupt.
When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate
interrupts.
lsb: 8
reset_value: '1'
width: 1
- ADC1_INTEN:
fields: !!omap
- ADINTEN:
access: rw
description: These bits allow control over which A/D channels generate interrupts
for conversion completion
lsb: 0
reset_value: '0'
width: 8
- ADGINTEN:
access: rw
description: When 1, enables the global DONE flag in ADDR to generate an interrupt.
When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate
interrupts.
lsb: 8
reset_value: '1'
width: 1
- ADC0_DR0:
fields: !!omap
- V_VREF:
access: r
description: When DONE is 1, this field contains a binary fraction representing
the voltage on the ADC0 pin divided by the reference voltage on the VDDA
pin
lsb: 6
reset_value: '0'
width: 10
- OVERRUN:
access: r
description: This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced the
result in the V_VREF bits in this register.
lsb: 30
reset_value: '0'
width: 1
- DONE:
access: r
description: This bit is set to 1 when an A/D conversion completes.
lsb: 31
reset_value: '0'
width: 1
- ADC1_DR0:
fields: !!omap
- V_VREF:
access: r
description: When DONE is 1, this field contains a binary fraction representing
the voltage on the ADC0 pin divided by the reference voltage on the VDDA
pin
lsb: 6
reset_value: '0'
width: 10
- OVERRUN:
access: r
description: This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced the
result in the V_VREF bits in this register.
lsb: 30
reset_value: '0'
width: 1
- DONE:
access: r
description: This bit is set to 1 when an A/D conversion completes.
lsb: 31
reset_value: '0'
width: 1
- ADC0_DR1:
fields: !!omap
- V_VREF:
access: r
description: When DONE is 1, this field contains a binary fraction representing
the voltage on the ADC1 pin divided by the reference voltage on the VDDA
pin
lsb: 6
reset_value: '0'
width: 10
- OVERRUN:
access: r
description: This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced the
result in the V_VREF bits in this register.
lsb: 30
reset_value: '0'
width: 1
- DONE:
access: r
description: This bit is set to 1 when an A/D conversion completes.
lsb: 31
reset_value: '0'
width: 1
- ADC1_DR1:
fields: !!omap
- V_VREF:
access: r
description: When DONE is 1, this field contains a binary fraction representing
the voltage on the ADC1 pin divided by the reference voltage on the VDDA
pin
lsb: 6
reset_value: '0'
width: 10
- OVERRUN:
access: r
description: This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced the
result in the V_VREF bits in this register.
lsb: 30
reset_value: '0'
width: 1
- DONE:
access: r
description: This bit is set to 1 when an A/D conversion completes.
lsb: 31
reset_value: '0'
width: 1
- ADC0_DR2:
fields: !!omap
- V_VREF:
access: r
description: When DONE is 1, this field contains a binary fraction representing
the voltage on the ADC2 pin divided by the reference voltage on the VDDA
pin
lsb: 6
reset_value: '0'
width: 10
- OVERRUN:
access: r
description: This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced the
result in the V_VREF bits in this register.
lsb: 30
reset_value: '0'
width: 1
- DONE:
access: r
description: This bit is set to 1 when an A/D conversion completes.
lsb: 31
reset_value: '0'
width: 1
- ADC1_DR2:
fields: !!omap
- V_VREF:
access: r
description: When DONE is 1, this field contains a binary fraction representing
the voltage on the ADC2 pin divided by the reference voltage on the VDDA
pin
lsb: 6
reset_value: '0'
width: 10
- OVERRUN:
access: r
description: This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced the
result in the V_VREF bits in this register.
lsb: 30
reset_value: '0'
width: 1
- DONE:
access: r
description: This bit is set to 1 when an A/D conversion completes.
lsb: 31
reset_value: '0'
width: 1
- ADC0_DR3:
fields: !!omap
- V_VREF:
access: r
description: When DONE is 1, this field contains a binary fraction representing
the voltage on the ADC3 pin divided by the reference voltage on the VDDA
pin
lsb: 6
reset_value: '0'
width: 10
- OVERRUN:
access: r
description: This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced the
result in the V_VREF bits in this register.
lsb: 30
reset_value: '0'
width: 1
- DONE:
access: r
description: This bit is set to 1 when an A/D conversion completes.
lsb: 31
reset_value: '0'
width: 1
- ADC1_DR3:
fields: !!omap
- V_VREF:
access: r
description: When DONE is 1, this field contains a binary fraction representing
the voltage on the ADC3 pin divided by the reference voltage on the VDDA
pin
lsb: 6
reset_value: '0'
width: 10
- OVERRUN:
access: r
description: This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced the
result in the V_VREF bits in this register.
lsb: 30
reset_value: '0'
width: 1
- DONE:
access: r
description: This bit is set to 1 when an A/D conversion completes.
lsb: 31
reset_value: '0'
width: 1
- ADC0_DR4:
fields: !!omap
- V_VREF:
access: r
description: When DONE is 1, this field contains a binary fraction representing
the voltage on the ADC4 pin divided by the reference voltage on the VDDA
pin
lsb: 6
reset_value: '0'
width: 10
- OVERRUN:
access: r
description: This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced the
result in the V_VREF bits in this register.
lsb: 30
reset_value: '0'
width: 1
- DONE:
access: r
description: This bit is set to 1 when an A/D conversion completes.
lsb: 31
reset_value: '0'
width: 1
- ADC1_DR4:
fields: !!omap
- V_VREF:
access: r
description: When DONE is 1, this field contains a binary fraction representing
the voltage on the ADC4 pin divided by the reference voltage on the VDDA
pin
lsb: 6
reset_value: '0'
width: 10
- OVERRUN:
access: r
description: This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced the
result in the V_VREF bits in this register.
lsb: 30
reset_value: '0'
width: 1
- DONE:
access: r
description: This bit is set to 1 when an A/D conversion completes.
lsb: 31
reset_value: '0'
width: 1
- ADC0_DR5:
fields: !!omap
- V_VREF:
access: r
description: When DONE is 1, this field contains a binary fraction representing
the voltage on the ADC5 pin divided by the reference voltage on the VDDA
pin
lsb: 6
reset_value: '0'
width: 10
- OVERRUN:
access: r
description: This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced the
result in the V_VREF bits in this register.
lsb: 30
reset_value: '0'
width: 1
- DONE:
access: r
description: This bit is set to 1 when an A/D conversion completes.
lsb: 31
reset_value: '0'
width: 1
- ADC1_DR5:
fields: !!omap
- V_VREF:
access: r
description: When DONE is 1, this field contains a binary fraction representing
the voltage on the ADC5 pin divided by the reference voltage on the VDDA
pin
lsb: 6
reset_value: '0'
width: 10
- OVERRUN:
access: r
description: This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced the
result in the V_VREF bits in this register.
lsb: 30
reset_value: '0'
width: 1
- DONE:
access: r
description: This bit is set to 1 when an A/D conversion completes.
lsb: 31
reset_value: '0'
width: 1
- ADC0_DR6:
fields: !!omap
- V_VREF:
access: r
description: When DONE is 1, this field contains a binary fraction representing
the voltage on the ADC6 pin divided by the reference voltage on the VDDA
pin
lsb: 6
reset_value: '0'
width: 10
- OVERRUN:
access: r
description: This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced the
result in the V_VREF bits in this register.
lsb: 30
reset_value: '0'
width: 1
- DONE:
access: r
description: This bit is set to 1 when an A/D conversion completes.
lsb: 31
reset_value: '0'
width: 1
- ADC1_DR6:
fields: !!omap
- V_VREF:
access: r
description: When DONE is 1, this field contains a binary fraction representing
the voltage on the ADC6 pin divided by the reference voltage on the VDDA
pin
lsb: 6
reset_value: '0'
width: 10
- OVERRUN:
access: r
description: This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced the
result in the V_VREF bits in this register.
lsb: 30
reset_value: '0'
width: 1
- DONE:
access: r
description: This bit is set to 1 when an A/D conversion completes.
lsb: 31
reset_value: '0'
width: 1
- ADC0_DR7:
fields: !!omap
- V_VREF:
access: r
description: When DONE is 1, this field contains a binary fraction representing
the voltage on the ADC7 pin divided by the reference voltage on the VDDA
pin
lsb: 6
reset_value: '0'
width: 10
- OVERRUN:
access: r
description: This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced the
result in the V_VREF bits in this register.
lsb: 30
reset_value: '0'
width: 1
- DONE:
access: r
description: This bit is set to 1 when an A/D conversion completes.
lsb: 31
reset_value: '0'
width: 1
- ADC1_DR7:
fields: !!omap
- V_VREF:
access: r
description: When DONE is 1, this field contains a binary fraction representing
the voltage on the ADC7 pin divided by the reference voltage on the VDDA
pin
lsb: 6
reset_value: '0'
width: 10
- OVERRUN:
access: r
description: This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced the
result in the V_VREF bits in this register.
lsb: 30
reset_value: '0'
width: 1
- DONE:
access: r
description: This bit is set to 1 when an A/D conversion completes.
lsb: 31
reset_value: '0'
width: 1
- ADC0_STAT:
fields: !!omap
- DONE:
access: r
description: These bits mirror the DONE status flags that appear in the result
register for each A/D channel.
lsb: 0
reset_value: '0'
width: 8
- OVERRUN:
access: r
description: These bits mirror the OVERRRUN status flags that appear in the
result register for each A/D channel.
lsb: 8
reset_value: '0'
width: 8
- ADINT:
access: r
description: This bit is the A/D interrupt flag. It is one when any of the
individual A/D channel Done flags is asserted and enabled to contribute
to the A/D interrupt via the ADINTEN register.
lsb: 16
reset_value: '0'
width: 1

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libopencm3/scripts/data/lpc43xx/atimer.yaml Normal file
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!!omap
- ATIMER_DOWNCOUNTER:
fields: !!omap
- CVAL:
access: rw
description: When equal to zero an interrupt is raised
lsb: 0
reset_value: '0'
width: 16
- ATIMER_PRESET:
fields: !!omap
- PRESETVAL:
access: rw
description: Value loaded in DOWNCOUNTER when DOWNCOUNTER equals zero
lsb: 0
reset_value: '0'
width: 16
- ATIMER_CLR_EN:
fields: !!omap
- CLR_EN:
access: w
description: Writing a 1 to this bit clears the interrupt enable bit in the
ENABLE register
lsb: 0
reset_value: '0'
width: 1
- ATIMER_SET_EN:
fields: !!omap
- SET_EN:
access: w
description: Writing a 1 to this bit sets the interrupt enable bit in the
ENABLE register
lsb: 0
reset_value: '0'
width: 1
- ATIMER_STATUS:
fields: !!omap
- STAT:
access: r
description: A 1 in this bit shows that the STATUS interrupt has been raised
lsb: 0
reset_value: '0'
width: 1
- ATIMER_ENABLE:
fields: !!omap
- ENA:
access: r
description: A 1 in this bit shows that the STATUS interrupt has been enabled
and that the STATUS interrupt request signal is asserted when STAT = 1 in
the STATUS register
lsb: 0
reset_value: '0'
width: 1
- ATIMER_CLR_STAT:
fields: !!omap
- CSTAT:
access: w
description: Writing a 1 to this bit clears the STATUS interrupt bit in the
STATUS register
lsb: 0
reset_value: '0'
width: 1
- ATIMER_SET_STAT:
fields: !!omap
- SSTAT:
access: w
description: Writing a 1 to this bit sets the STATUS interrupt bit in the
STATUS register
lsb: 0
reset_value: '0'
width: 1

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libopencm3/scripts/data/lpc43xx/ccu.yaml Normal file
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libopencm3/scripts/data/lpc43xx/cgu.yaml Normal file
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!!omap
- CGU_FREQ_MON:
fields: !!omap
- RCNT:
access: rw
description: 9-bit reference clock-counter value
lsb: 0
reset_value: '0'
width: 9
- FCNT:
access: r
description: 14-bit selected clock-counter value
lsb: 9
reset_value: '0'
width: 14
- MEAS:
access: rw
description: Measure frequency
lsb: 23
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock-source selection for the clock to be measured
lsb: 24
reset_value: '0'
width: 5
- CGU_XTAL_OSC_CTRL:
fields: !!omap
- ENABLE:
access: rw
description: Oscillator-pad enable
lsb: 0
reset_value: '1'
width: 1
- BYPASS:
access: rw
description: Configure crystal operation or external-clock input pin XTAL1
lsb: 1
reset_value: '0'
width: 1
- HF:
access: rw
description: Select frequency range
lsb: 2
reset_value: '1'
width: 1
- CGU_PLL0USB_STAT:
fields: !!omap
- LOCK:
access: r
description: PLL0 lock indicator
lsb: 0
reset_value: '0'
width: 1
- FR:
access: r
description: PLL0 free running indicator
lsb: 1
reset_value: '0'
width: 1
- CGU_PLL0USB_CTRL:
fields: !!omap
- PD:
access: rw
description: PLL0 power down
lsb: 0
reset_value: '1'
width: 1
- BYPASS:
access: rw
description: Input clock bypass control
lsb: 1
reset_value: '1'
width: 1
- DIRECTI:
access: rw
description: PLL0 direct input
lsb: 2
reset_value: '0'
width: 1
- DIRECTO:
access: rw
description: PLL0 direct output
lsb: 3
reset_value: '0'
width: 1
- CLKEN:
access: rw
description: PLL0 clock enable
lsb: 4
reset_value: '0'
width: 1
- FRM:
access: rw
description: Free running mode
lsb: 6
reset_value: '0'
width: 1
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_PLL0USB_MDIV:
fields: !!omap
- MDEC:
access: rw
description: Decoded M-divider coefficient value
lsb: 0
reset_value: '0x5B6A'
width: 17
- SELP:
access: rw
description: Bandwidth select P value
lsb: 17
reset_value: '0x1C'
width: 5
- SELI:
access: rw
description: Bandwidth select I value
lsb: 22
reset_value: '0x17'
width: 6
- SELR:
access: rw
description: Bandwidth select R value
lsb: 28
reset_value: '0x0'
width: 4
- CGU_PLL0USB_NP_DIV:
fields: !!omap
- PDEC:
access: rw
description: Decoded P-divider coefficient value
lsb: 0
reset_value: '0x02'
width: 7
- NDEC:
access: rw
description: Decoded N-divider coefficient value
lsb: 12
reset_value: '0xB1'
width: 10
- CGU_PLL0AUDIO_STAT:
fields: !!omap
- LOCK:
access: r
description: PLL0 lock indicator
lsb: 0
reset_value: '0'
width: 1
- FR:
access: r
description: PLL0 free running indicator
lsb: 1
reset_value: '0'
width: 1
- CGU_PLL0AUDIO_CTRL:
fields: !!omap
- PD:
access: rw
description: PLL0 power down
lsb: 0
reset_value: '1'
width: 1
- BYPASS:
access: rw
description: Input clock bypass control
lsb: 1
reset_value: '1'
width: 1
- DIRECTI:
access: rw
description: PLL0 direct input
lsb: 2
reset_value: '0'
width: 1
- DIRECTO:
access: rw
description: PLL0 direct output
lsb: 3
reset_value: '0'
width: 1
- CLKEN:
access: rw
description: PLL0 clock enable
lsb: 4
reset_value: '0'
width: 1
- FRM:
access: rw
description: Free running mode
lsb: 6
reset_value: '0'
width: 1
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- PLLFRACT_REQ:
access: rw
description: Fractional PLL word write request
lsb: 12
reset_value: '0'
width: 1
- SEL_EXT:
access: rw
description: Select fractional divider
lsb: 13
reset_value: '0'
width: 1
- MOD_PD:
access: rw
description: Sigma-Delta modulator power-down
lsb: 14
reset_value: '1'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_PLL0AUDIO_MDIV:
fields: !!omap
- MDEC:
access: rw
description: Decoded M-divider coefficient value
lsb: 0
reset_value: '0x5B6A'
width: 17
- CGU_PLL0AUDIO_NP_DIV:
fields: !!omap
- PDEC:
access: rw
description: Decoded P-divider coefficient value
lsb: 0
reset_value: '0x02'
width: 7
- NDEC:
access: rw
description: Decoded N-divider coefficient value
lsb: 12
reset_value: '0xB1'
width: 10
- CGU_PLLAUDIO_FRAC:
fields: !!omap
- PLLFRACT_CTRL:
access: rw
description: PLL fractional divider control word
lsb: 0
reset_value: '0x00'
width: 22
- CGU_PLL1_STAT:
fields: !!omap
- LOCK:
access: r
description: PLL1 lock indicator
lsb: 0
reset_value: '0'
width: 1
- CGU_PLL1_CTRL:
fields: !!omap
- PD:
access: rw
description: PLL1 power down
lsb: 0
reset_value: '1'
width: 1
- BYPASS:
access: rw
description: Input clock bypass control
lsb: 1
reset_value: '1'
width: 1
- FBSEL:
access: rw
description: PLL feedback select
lsb: 6
reset_value: '0'
width: 1
- DIRECT:
access: rw
description: PLL direct CCO output
lsb: 7
reset_value: '0'
width: 1
- PSEL:
access: rw
description: Post-divider division ratio P
lsb: 8
reset_value: '0x1'
width: 2
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- NSEL:
access: rw
description: Pre-divider division ratio N
lsb: 12
reset_value: '0x2'
width: 2
- MSEL:
access: rw
description: Feedback-divider division ratio (M)
lsb: 16
reset_value: '0x18'
width: 8
- CLK_SEL:
access: rw
description: Clock-source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_IDIVA_CTRL:
fields: !!omap
- PD:
access: rw
description: Integer divider power down
lsb: 0
reset_value: '0'
width: 1
- IDIV:
access: rw
description: Integer divider A divider value (1/(IDIV + 1))
lsb: 2
reset_value: '0x0'
width: 2
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_IDIVB_CTRL:
fields: !!omap
- PD:
access: rw
description: Integer divider power down
lsb: 0
reset_value: '0'
width: 1
- IDIV:
access: rw
description: Integer divider B divider value (1/(IDIV + 1))
lsb: 2
reset_value: '0x0'
width: 4
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_IDIVC_CTRL:
fields: !!omap
- PD:
access: rw
description: Integer divider power down
lsb: 0
reset_value: '0'
width: 1
- IDIV:
access: rw
description: Integer divider C divider value (1/(IDIV + 1))
lsb: 2
reset_value: '0x0'
width: 4
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_IDIVD_CTRL:
fields: !!omap
- PD:
access: rw
description: Integer divider power down
lsb: 0
reset_value: '0'
width: 1
- IDIV:
access: rw
description: Integer divider D divider value (1/(IDIV + 1))
lsb: 2
reset_value: '0x0'
width: 4
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_IDIVE_CTRL:
fields: !!omap
- PD:
access: rw
description: Integer divider power down
lsb: 0
reset_value: '0'
width: 1
- IDIV:
access: rw
description: Integer divider E divider value (1/(IDIV + 1))
lsb: 2
reset_value: '0x00'
width: 8
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_BASE_SAFE_CLK:
fields: !!omap
- PD:
access: r
description: Output stage power down
lsb: 0
reset_value: '0'
width: 1
- AUTOBLOCK:
access: r
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: r
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_BASE_USB0_CLK:
fields: !!omap
- PD:
access: rw
description: Output stage power down
lsb: 0
reset_value: '0'
width: 1
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x07'
width: 5
- CGU_BASE_PERIPH_CLK:
fields: !!omap
- PD:
access: rw
description: Output stage power down
lsb: 0
reset_value: '0'
width: 1
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_BASE_USB1_CLK:
fields: !!omap
- PD:
access: rw
description: Output stage power down
lsb: 0
reset_value: '0'
width: 1
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_BASE_M4_CLK:
fields: !!omap
- PD:
access: rw
description: Output stage power down
lsb: 0
reset_value: '0'
width: 1
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_BASE_SPIFI_CLK:
fields: !!omap
- PD:
access: rw
description: Output stage power down
lsb: 0
reset_value: '0'
width: 1
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_BASE_SPI_CLK:
fields: !!omap
- PD:
access: rw
description: Output stage power down
lsb: 0
reset_value: '0'
width: 1
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_BASE_PHY_RX_CLK:
fields: !!omap
- PD:
access: rw
description: Output stage power down
lsb: 0
reset_value: '0'
width: 1
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_BASE_PHY_TX_CLK:
fields: !!omap
- PD:
access: rw
description: Output stage power down
lsb: 0
reset_value: '0'
width: 1
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_BASE_APB1_CLK:
fields: !!omap
- PD:
access: rw
description: Output stage power down
lsb: 0
reset_value: '0'
width: 1
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_BASE_APB3_CLK:
fields: !!omap
- PD:
access: rw
description: Output stage power down
lsb: 0
reset_value: '0'
width: 1
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_BASE_LCD_CLK:
fields: !!omap
- PD:
access: rw
description: Output stage power down
lsb: 0
reset_value: '0'
width: 1
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_BASE_VADC_CLK:
fields: !!omap
- PD:
access: rw
description: Output stage power down
lsb: 0
reset_value: '0'
width: 1
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_BASE_SDIO_CLK:
fields: !!omap
- PD:
access: rw
description: Output stage power down
lsb: 0
reset_value: '0'
width: 1
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_BASE_SSP0_CLK:
fields: !!omap
- PD:
access: rw
description: Output stage power down
lsb: 0
reset_value: '0'
width: 1
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_BASE_SSP1_CLK:
fields: !!omap
- PD:
access: rw
description: Output stage power down
lsb: 0
reset_value: '0'
width: 1
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_BASE_UART0_CLK:
fields: !!omap
- PD:
access: rw
description: Output stage power down
lsb: 0
reset_value: '0'
width: 1
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_BASE_UART1_CLK:
fields: !!omap
- PD:
access: rw
description: Output stage power down
lsb: 0
reset_value: '0'
width: 1
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_BASE_UART2_CLK:
fields: !!omap
- PD:
access: rw
description: Output stage power down
lsb: 0
reset_value: '0'
width: 1
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_BASE_UART3_CLK:
fields: !!omap
- PD:
access: rw
description: Output stage power down
lsb: 0
reset_value: '0'
width: 1
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_BASE_OUT_CLK:
fields: !!omap
- PD:
access: rw
description: Output stage power down
lsb: 0
reset_value: '0'
width: 1
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_BASE_APLL_CLK:
fields: !!omap
- PD:
access: rw
description: Output stage power down
lsb: 0
reset_value: '0'
width: 1
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_BASE_CGU_OUT0_CLK:
fields: !!omap
- PD:
access: rw
description: Output stage power down
lsb: 0
reset_value: '0'
width: 1
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5
- CGU_BASE_CGU_OUT1_CLK:
fields: !!omap
- PD:
access: rw
description: Output stage power down
lsb: 0
reset_value: '0'
width: 1
- AUTOBLOCK:
access: rw
description: Block clock automatically during frequency change
lsb: 11
reset_value: '0'
width: 1
- CLK_SEL:
access: rw
description: Clock source selection
lsb: 24
reset_value: '0x01'
width: 5

312
libopencm3/scripts/data/lpc43xx/creg.yaml Normal file
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@@ -0,0 +1,312 @@
!!omap
- CREG_CREG0:
fields: !!omap
- EN1KHZ:
access: rw
description: Enable 1 kHz output
lsb: 0
reset_value: '0'
width: 1
- EN32KHZ:
access: rw
description: Enable 32 kHz output
lsb: 1
reset_value: '0'
width: 1
- RESET32KHZ:
access: rw
description: 32 kHz oscillator reset
lsb: 2
reset_value: '1'
width: 1
- PD32KHZ:
access: rw
description: 32 kHz power control
lsb: 3
reset_value: '1'
width: 1
- USB0PHY:
access: rw
description: USB0 PHY power control
lsb: 5
reset_value: '1'
width: 1
- ALARMCTRL:
access: rw
description: RTC_ALARM pin output control
lsb: 6
reset_value: '0'
width: 2
- BODLVL1:
access: rw
description: BOD trip level to generate an interrupt
lsb: 8
reset_value: '0x3'
width: 2
- BODLVL2:
access: rw
description: BOD trip level to generate a reset
lsb: 10
reset_value: '0x3'
width: 2
- SAMPLECTRL:
access: rw
description: SAMPLE pin input/output control
lsb: 12
reset_value: '0'
width: 2
- WAKEUP0CTRL:
access: rw
description: WAKEUP0 pin input/output control
lsb: 14
reset_value: '0'
width: 2
- WAKEUP1CTRL:
access: rw
description: WAKEUP1 pin input/output control
lsb: 16
reset_value: '0'
width: 2
- CREG_M4MEMMAP:
fields: !!omap
- M4MAP:
access: rw
description: Shadow address when accessing memory at address 0x00000000
lsb: 12
reset_value: '0x10400000'
width: 20
- CREG_CREG5:
fields: !!omap
- M4TAPSEL:
access: rw
description: JTAG debug select for M4 core
lsb: 6
reset_value: '1'
width: 1
- M0APPTAPSEL:
access: rw
description: JTAG debug select for M0 co-processor
lsb: 9
reset_value: '1'
width: 1
- CREG_DMAMUX:
fields: !!omap
- DMAMUXPER0:
access: rw
description: Select DMA to peripheral connection for DMA peripheral 0
lsb: 0
reset_value: '0'
width: 2
- DMAMUXPER1:
access: rw
description: Select DMA to peripheral connection for DMA peripheral 1
lsb: 2
reset_value: '0'
width: 2
- DMAMUXPER2:
access: rw
description: Select DMA to peripheral connection for DMA peripheral 2
lsb: 4
reset_value: '0'
width: 2
- DMAMUXPER3:
access: rw
description: Select DMA to peripheral connection for DMA peripheral 3
lsb: 6
reset_value: '0'
width: 2
- DMAMUXPER4:
access: rw
description: Select DMA to peripheral connection for DMA peripheral 4
lsb: 8
reset_value: '0'
width: 2
- DMAMUXPER5:
access: rw
description: Select DMA to peripheral connection for DMA peripheral 5
lsb: 10
reset_value: '0'
width: 2
- DMAMUXPER6:
access: rw
description: Select DMA to peripheral connection for DMA peripheral 6
lsb: 12
reset_value: '0'
width: 2
- DMAMUXPER7:
access: rw
description: Select DMA to peripheral connection for DMA peripheral 7
lsb: 14
reset_value: '0'
width: 2
- DMAMUXPER8:
access: rw
description: Select DMA to peripheral connection for DMA peripheral 8
lsb: 16
reset_value: '0'
width: 2
- DMAMUXPER9:
access: rw
description: Select DMA to peripheral connection for DMA peripheral 9
lsb: 18
reset_value: '0'
width: 2
- DMAMUXPER10:
access: rw
description: Select DMA to peripheral connection for DMA peripheral 10
lsb: 20
reset_value: '0'
width: 2
- DMAMUXPER11:
access: rw
description: Select DMA to peripheral connection for DMA peripheral 11
lsb: 22
reset_value: '0'
width: 2
- DMAMUXPER12:
access: rw
description: Select DMA to peripheral connection for DMA peripheral 12
lsb: 24
reset_value: '0'
width: 2
- DMAMUXPER13:
access: rw
description: Select DMA to peripheral connection for DMA peripheral 13
lsb: 26
reset_value: '0'
width: 2
- DMAMUXPER14:
access: rw
description: Select DMA to peripheral connection for DMA peripheral 14
lsb: 28
reset_value: '0'
width: 2
- DMAMUXPER15:
access: rw
description: Select DMA to peripheral connection for DMA peripheral 15
lsb: 30
reset_value: '0'
width: 2
- CREG_FLASHCFGA:
fields: !!omap
- FLASHTIM:
access: rw
description: Flash access time. The value of this field plus 1 gives the number
of BASE_M4_CLK clocks used for a flash access
lsb: 12
reset_value: ''
width: 4
- POW:
access: rw
description: Flash bank A power control
lsb: 31
reset_value: '1'
width: 1
- CREG_FLASHCFGB:
fields: !!omap
- FLASHTIM:
access: rw
description: Flash access time. The value of this field plus 1 gives the number
of BASE_M4_CLK clocks used for a flash access
lsb: 12
reset_value: ''
width: 4
- POW:
access: rw
description: Flash bank B power control
lsb: 31
reset_value: '1'
width: 1
- CREG_ETBCFG:
fields: !!omap
- ETB:
access: rw
description: Select SRAM interface
lsb: 0
reset_value: '1'
width: 1
- CREG_CREG6:
fields: !!omap
- ETHMODE:
access: rw
description: Selects the Ethernet mode. Reset the ethernet after changing
the PHY interface
lsb: 0
reset_value: ''
width: 3
- CTOUTCTRL:
access: rw
description: Selects the functionality of the SCT outputs
lsb: 4
reset_value: '0'
width: 1
- I2S0_TX_SCK_IN_SEL:
access: rw
description: I2S0_TX_SCK input select
lsb: 12
reset_value: '0'
width: 1
- I2S0_RX_SCK_IN_SEL:
access: rw
description: I2S0_RX_SCK input select
lsb: 13
reset_value: '0'
width: 1
- I2S1_TX_SCK_IN_SEL:
access: rw
description: I2S1_TX_SCK input select
lsb: 14
reset_value: '0'
width: 1
- I2S1_RX_SCK_IN_SEL:
access: rw
description: I2S1_RX_SCK input select
lsb: 15
reset_value: '0'
width: 1
- EMC_CLK_SEL:
access: rw
description: EMC_CLK divided clock select
lsb: 16
reset_value: '0'
width: 1
- CREG_M4TXEVENT:
fields: !!omap
- TXEVCLR:
access: rw
description: Cortex-M4 TXEV event
lsb: 0
reset_value: '0'
width: 1
- CREG_M0TXEVENT:
fields: !!omap
- TXEVCLR:
access: rw
description: Cortex-M0 TXEV event
lsb: 0
reset_value: '0'
width: 1
- CREG_M0APPMEMMAP:
fields: !!omap
- M0APPMAP:
access: rw
description: Shadow address when accessing memory at address 0x00000000
lsb: 12
reset_value: '0x20000000'
width: 20
- CREG_USB0FLADJ:
fields: !!omap
- FLTV:
access: rw
description: Frame length timing value
lsb: 0
reset_value: '0x20'
width: 6
- CREG_USB1FLADJ:
fields: !!omap
- FLTV:
access: rw
description: Frame length timing value
lsb: 0
reset_value: '0x20'
width: 6

36
libopencm3/scripts/data/lpc43xx/csv2yaml.py Executable file
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#!/usr/bin/env python2
import sys
import yaml
import csv
from collections import OrderedDict
def convert_file(fname):
reader = csv.reader(open(fname, 'r'))
registers = OrderedDict()
for register_name, lsb, width, field_name, description, reset_value, access in reader:
if register_name not in registers:
registers[register_name] = {
'fields': OrderedDict(),
}
register = registers[register_name]
fields = register['fields']
if field_name in fields:
raise RuntimeError('Duplicate field name "%s" in register "%s"' %
field_name, register_name)
else:
fields[field_name] = {
'lsb': int(lsb),
'width': int(width),
'description': description,
'reset_value': reset_value,
'access': access,
}
with open(fname.replace('.csv', '.yaml'), 'w') as out_file:
yaml.dump(registers, out_file, default_flow_style=False)
for fname in sys.argv[1:]:
convert_file(fname)

959
libopencm3/scripts/data/lpc43xx/eventrouter.yaml Normal file
View File

@@ -0,0 +1,959 @@
!!omap
- EVENTROUTER_HILO:
fields: !!omap
- WAKEUP0_L:
access: rw
description: Level detect mode for WAKEUP0 event
lsb: 0
reset_value: '0'
width: 1
- WAKEUP1_L:
access: rw
description: Level detect mode for WAKEUP1 event
lsb: 1
reset_value: '0'
width: 1
- WAKEUP2_L:
access: rw
description: Level detect mode for WAKEUP2 event
lsb: 2
reset_value: '0'
width: 1
- WAKEUP3_L:
access: rw
description: Level detect mode for WAKEUP3 event
lsb: 3
reset_value: '0'
width: 1
- ATIMER_L:
access: rw
description: Level detect mode for alarm timer event
lsb: 4
reset_value: '0'
width: 1
- RTC_L:
access: rw
description: Level detect mode for RTC event
lsb: 5
reset_value: '0'
width: 1
- BOD_L:
access: rw
description: Level detect mode for BOD event
lsb: 6
reset_value: '0'
width: 1
- WWDT_L:
access: rw
description: Level detect mode for WWDT event
lsb: 7
reset_value: '0'
width: 1
- ETH_L:
access: rw
description: Level detect mode for Ethernet event
lsb: 8
reset_value: '0'
width: 1
- USB0_L:
access: rw
description: Level detect mode for USB0 event
lsb: 9
reset_value: '0'
width: 1
- USB1_L:
access: rw
description: Level detect mode for USB1 event
lsb: 10
reset_value: '0'
width: 1
- SDMMC_L:
access: rw
description: Level detect mode for SD/MMC event
lsb: 11
reset_value: '0'
width: 1
- CAN_L:
access: rw
description: Level detect mode for C_CAN event
lsb: 12
reset_value: '0'
width: 1
- TIM2_L:
access: rw
description: Level detect mode for combined timer output 2 event
lsb: 13
reset_value: '0'
width: 1
- TIM6_L:
access: rw
description: Level detect mode for combined timer output 6 event
lsb: 14
reset_value: '0'
width: 1
- QEI_L:
access: rw
description: Level detect mode for QEI event
lsb: 15
reset_value: '0'
width: 1
- TIM14_L:
access: rw
description: Level detect mode for combined timer output 14 event
lsb: 16
reset_value: '0'
width: 1
- RESET_L:
access: rw
description: Level detect mode for Reset
lsb: 19
reset_value: '0'
width: 1
- EVENTROUTER_EDGE:
fields: !!omap
- WAKEUP0_E:
access: rw
description: Edge/Level detect mode for WAKEUP0 event
lsb: 0
reset_value: '0'
width: 1
- WAKEUP1_E:
access: rw
description: Edge/Level detect mode for WAKEUP1 event
lsb: 1
reset_value: '0'
width: 1
- WAKEUP2_E:
access: rw
description: Edge/Level detect mode for WAKEUP2 event
lsb: 2
reset_value: '0'
width: 1
- WAKEUP3_E:
access: rw
description: Edge/Level detect mode for WAKEUP3 event
lsb: 3
reset_value: '0'
width: 1
- ATIMER_E:
access: rw
description: Edge/Level detect mode for alarm timer event
lsb: 4
reset_value: '0'
width: 1
- RTC_E:
access: rw
description: Edge/Level detect mode for RTC event
lsb: 5
reset_value: '0'
width: 1
- BOD_E:
access: rw
description: Edge/Level detect mode for BOD event
lsb: 6
reset_value: '0'
width: 1
- WWDT_E:
access: rw
description: Edge/Level detect mode for WWDT event
lsb: 7
reset_value: '0'
width: 1
- ETH_E:
access: rw
description: Edge/Level detect mode for Ethernet event
lsb: 8
reset_value: '0'
width: 1
- USB0_E:
access: rw
description: Edge/Level detect mode for USB0 event
lsb: 9
reset_value: '0'
width: 1
- USB1_E:
access: rw
description: Edge/Level detect mode for USB1 event
lsb: 10
reset_value: '0'
width: 1
- SDMMC_E:
access: rw
description: Edge/Level detect mode for SD/MMC event
lsb: 11
reset_value: '0'
width: 1
- CAN_E:
access: rw
description: Edge/Level detect mode for C_CAN event
lsb: 12
reset_value: '0'
width: 1
- TIM2_E:
access: rw
description: Edge/Level detect mode for combined timer output 2 event
lsb: 13
reset_value: '0'
width: 1
- TIM6_E:
access: rw
description: Edge/Level detect mode for combined timer output 6 event
lsb: 14
reset_value: '0'
width: 1
- QEI_E:
access: rw
description: Edge/Level detect mode for QEI event
lsb: 15
reset_value: '0'
width: 1
- TIM14_E:
access: rw
description: Edge/Level detect mode for combined timer output 14 event
lsb: 16
reset_value: '0'
width: 1
- RESET_E:
access: rw
description: Edge/Level detect mode for Reset
lsb: 19
reset_value: '0'
width: 1
- EVENTROUTER_CLR_EN:
fields: !!omap
- WAKEUP0_CLREN:
access: w
description: Writing a 1 to this bit clears the event enable bit 0 in the
ENABLE register
lsb: 0
reset_value: '0'
width: 1
- WAKEUP1_CLREN:
access: w
description: Writing a 1 to this bit clears the event enable bit 1 in the
ENABLE register
lsb: 1
reset_value: '0'
width: 1
- WAKEUP2_CLREN:
access: w
description: Writing a 1 to this bit clears the event enable bit 2 in the
ENABLE register
lsb: 2
reset_value: '0'
width: 1
- WAKEUP3_CLREN:
access: w
description: Writing a 1 to this bit clears the event enable bit 3 in the
ENABLE register
lsb: 3
reset_value: '0'
width: 1
- ATIMER_CLREN:
access: w
description: Writing a 1 to this bit clears the event enable bit 4 in the
ENABLE register
lsb: 4
reset_value: '0'
width: 1
- RTC_CLREN:
access: w
description: Writing a 1 to this bit clears the event enable bit 5 in the
ENABLE register
lsb: 5
reset_value: '0'
width: 1
- BOD_CLREN:
access: w
description: Writing a 1 to this bit clears the event enable bit 6 in the
ENABLE register
lsb: 6
reset_value: '0'
width: 1
- WWDT_CLREN:
access: w
description: Writing a 1 to this bit clears the event enable bit 7 in the
ENABLE register
lsb: 7
reset_value: '0'
width: 1
- ETH_CLREN:
access: w
description: Writing a 1 to this bit clears the event enable bit 8 in the
ENABLE register
lsb: 8
reset_value: '0'
width: 1
- USB0_CLREN:
access: w
description: Writing a 1 to this bit clears the event enable bit 9 in the
ENABLE register
lsb: 9
reset_value: '0'
width: 1
- USB1_CLREN:
access: w
description: Writing a 1 to this bit clears the event enable bit 10 in the
ENABLE register
lsb: 10
reset_value: '0'
width: 1
- SDMCC_CLREN:
access: w
description: Writing a 1 to this bit clears the event enable bit 11 in the
ENABLE register
lsb: 11
reset_value: '0'
width: 1
- CAN_CLREN:
access: w
description: Writing a 1 to this bit clears the event enable bit 12 in the
ENABLE register
lsb: 12
reset_value: '0'
width: 1
- TIM2_CLREN:
access: w
description: Writing a 1 to this bit clears the event enable bit 13 in the
ENABLE register
lsb: 13
reset_value: '0'
width: 1
- TIM6_CLREN:
access: w
description: Writing a 1 to this bit clears the event enable bit 14 in the
ENABLE register
lsb: 14
reset_value: '0'
width: 1
- QEI_CLREN:
access: w
description: Writing a 1 to this bit clears the event enable bit 15 in the
ENABLE register
lsb: 15
reset_value: '0'
width: 1
- TIM14_CLREN:
access: w
description: Writing a 1 to this bit clears the event enable bit 16 in the
ENABLE register
lsb: 16
reset_value: '0'
width: 1
- RESET_CLREN:
access: w
description: Writing a 1 to this bit clears the event enable bit 19 in the
ENABLE register
lsb: 19
reset_value: '0'
width: 1
- EVENTROUTER_SET_EN:
fields: !!omap
- WAKEUP0_SETEN:
access: w
description: Writing a 1 to this bit sets the event enable bit 0 in the ENABLE
register
lsb: 0
reset_value: '0'
width: 1
- WAKEUP1_SETEN:
access: w
description: Writing a 1 to this bit sets the event enable bit 1 in the ENABLE
register
lsb: 1
reset_value: '0'
width: 1
- WAKEUP2_SETEN:
access: w
description: Writing a 1 to this bit sets the event enable bit 2 in the ENABLE
register
lsb: 2
reset_value: '0'
width: 1
- WAKEUP3_SETEN:
access: w
description: Writing a 1 to this bit sets the event enable bit 3 in the ENABLE
register
lsb: 3
reset_value: '0'
width: 1
- ATIMER_SETEN:
access: w
description: Writing a 1 to this bit sets the event enable bit 4 in the ENABLE
register
lsb: 4
reset_value: '0'
width: 1
- RTC_SETEN:
access: w
description: Writing a 1 to this bit sets the event enable bit 5 in the ENABLE
register
lsb: 5
reset_value: '0'
width: 1
- BOD_SETEN:
access: w
description: Writing a 1 to this bit sets the event enable bit 6 in the ENABLE
register
lsb: 6
reset_value: '0'
width: 1
- WWDT_SETEN:
access: w
description: Writing a 1 to this bit sets the event enable bit 7 in the ENABLE
register
lsb: 7
reset_value: '0'
width: 1
- ETH_SETEN:
access: w
description: Writing a 1 to this bit sets the event enable bit 8 in the ENABLE
register
lsb: 8
reset_value: '0'
width: 1
- USB0_SETEN:
access: w
description: Writing a 1 to this bit sets the event enable bit 9 in the ENABLE
register
lsb: 9
reset_value: '0'
width: 1
- USB1_SETEN:
access: w
description: Writing a 1 to this bit sets the event enable bit 10 in the ENABLE
register
lsb: 10
reset_value: '0'
width: 1
- SDMCC_SETEN:
access: w
description: Writing a 1 to this bit sets the event enable bit 11 in the ENABLE
register
lsb: 11
reset_value: '0'
width: 1
- CAN_SETEN:
access: w
description: Writing a 1 to this bit sets the event enable bit 12 in the ENABLE
register
lsb: 12
reset_value: '0'
width: 1
- TIM2_SETEN:
access: w
description: Writing a 1 to this bit sets the event enable bit 13 in the ENABLE
register
lsb: 13
reset_value: '0'
width: 1
- TIM6_SETEN:
access: w
description: Writing a 1 to this bit sets the event enable bit 14 in the ENABLE
register
lsb: 14
reset_value: '0'
width: 1
- QEI_SETEN:
access: w
description: Writing a 1 to this bit sets the event enable bit 15 in the ENABLE
register
lsb: 15
reset_value: '0'
width: 1
- TIM14_SETEN:
access: w
description: Writing a 1 to this bit sets the event enable bit 16 in the ENABLE
register
lsb: 16
reset_value: '0'
width: 1
- RESET_SETEN:
access: w
description: Writing a 1 to this bit sets the event enable bit 19 in the ENABLE
register
lsb: 19
reset_value: '0'
width: 1
- EVENTROUTER_STATUS:
fields: !!omap
- WAKEUP0_ST:
access: r
description: A 1 in this bit shows that the WAKEUP0 event has been raised
lsb: 0
reset_value: '1'
width: 1
- WAKEUP1_ST:
access: r
description: A 1 in this bit shows that the WAKEUP1 event has been raised
lsb: 1
reset_value: '1'
width: 1
- WAKEUP2_ST:
access: r
description: A 1 in this bit shows that the WAKEUP2 event has been raised
lsb: 2
reset_value: '1'
width: 1
- WAKEUP3_ST:
access: r
description: A 1 in this bit shows that the WAKEUP3 event has been raised
lsb: 3
reset_value: '1'
width: 1
- ATIMER_ST:
access: r
description: A 1 in this bit shows that the ATIMER event has been raised
lsb: 4
reset_value: '1'
width: 1
- RTC_ST:
access: r
description: A 1 in this bit shows that the RTC event has been raised
lsb: 5
reset_value: '1'
width: 1
- BOD_ST:
access: r
description: A 1 in this bit shows that the BOD event has been raised
lsb: 6
reset_value: '1'
width: 1
- WWDT_ST:
access: r
description: A 1 in this bit shows that the WWDT event has been raised
lsb: 7
reset_value: '1'
width: 1
- ETH_ST:
access: r
description: A 1 in this bit shows that the ETH event has been raised
lsb: 8
reset_value: '1'
width: 1
- USB0_ST:
access: r
description: A 1 in this bit shows that the USB0 event has been raised
lsb: 9
reset_value: '1'
width: 1
- USB1_ST:
access: r
description: A 1 in this bit shows that the USB1 event has been raised
lsb: 10
reset_value: '1'
width: 1
- SDMMC_ST:
access: r
description: A 1 in this bit shows that the SDMMC event has been raised
lsb: 11
reset_value: '1'
width: 1
- CAN_ST:
access: r
description: A 1 in this bit shows that the CAN event has been raised
lsb: 12
reset_value: '1'
width: 1
- TIM2_ST:
access: r
description: A 1 in this bit shows that the combined timer 2 output event
has been raised
lsb: 13
reset_value: '1'
width: 1
- TIM6_ST:
access: r
description: A 1 in this bit shows that the combined timer 6 output event
has been raised
lsb: 14
reset_value: '1'
width: 1
- QEI_ST:
access: r
description: A 1 in this bit shows that the QEI event has been raised
lsb: 15
reset_value: '1'
width: 1
- TIM14_ST:
access: r
description: A 1 in this bit shows that the combined timer 14 output event
has been raised
lsb: 16
reset_value: '1'
width: 1
- RESET_ST:
access: r
description: A 1 in this bit shows that the reset event has been raised
lsb: 19
reset_value: '1'
width: 1
- EVENTROUTER_ENABLE:
fields: !!omap
- WAKEUP0_EN:
access: r
description: A 1 in this bit shows that the WAKEUP0 event has been enabled
lsb: 0
reset_value: '0'
width: 1
- WAKEUP1_EN:
access: r
description: A 1 in this bit shows that the WAKEUP1 event has been enabled
lsb: 1
reset_value: '0'
width: 1
- WAKEUP2_EN:
access: r
description: A 1 in this bit shows that the WAKEUP2 event has been enabled
lsb: 2
reset_value: '0'
width: 1
- WAKEUP3_EN:
access: r
description: A 1 in this bit shows that the WAKEUP3 event has been enabled
lsb: 3
reset_value: '0'
width: 1
- ATIMER_EN:
access: r
description: A 1 in this bit shows that the ATIMER event has been enabled
lsb: 4
reset_value: '0'
width: 1
- RTC_EN:
access: r
description: A 1 in this bit shows that the RTC event has been enabled
lsb: 5
reset_value: '0'
width: 1
- BOD_EN:
access: r
description: A 1 in this bit shows that the BOD event has been enabled
lsb: 6
reset_value: '0'
width: 1
- WWDT_EN:
access: r
description: A 1 in this bit shows that the WWDT event has been enabled
lsb: 7
reset_value: '0'
width: 1
- ETH_EN:
access: r
description: A 1 in this bit shows that the ETH event has been enabled
lsb: 8
reset_value: '0'
width: 1
- USB0_EN:
access: r
description: A 1 in this bit shows that the USB0 event has been enabled
lsb: 9
reset_value: '0'
width: 1
- USB1_EN:
access: r
description: A 1 in this bit shows that the USB1 event has been enabled
lsb: 10
reset_value: '0'
width: 1
- SDMMC_EN:
access: r
description: A 1 in this bit shows that the SDMMC event has been enabled
lsb: 11
reset_value: '0'
width: 1
- CAN_EN:
access: r
description: A 1 in this bit shows that the CAN event has been enabled
lsb: 12
reset_value: '0'
width: 1
- TIM2_EN:
access: r
description: A 1 in this bit shows that the combined timer 2 output event
has been enabled
lsb: 13
reset_value: '0'
width: 1
- TIM6_EN:
access: r
description: A 1 in this bit shows that the combined timer 6 output event
has been enabled
lsb: 14
reset_value: '0'
width: 1
- QEI_EN:
access: r
description: A 1 in this bit shows that the QEI event has been enabled
lsb: 15
reset_value: '0'
width: 1
- TIM14_EN:
access: r
description: A 1 in this bit shows that the combined timer 14 output event
has been enabled
lsb: 16
reset_value: '0'
width: 1
- RESET_EN:
access: r
description: A 1 in this bit shows that the reset event has been enabled
lsb: 19
reset_value: '0'
width: 1
- EVENTROUTER_CLR_STAT:
fields: !!omap
- WAKEUP0_CLRST:
access: w
description: Writing a 1 to this bit clears the STATUS event bit 0 in the
STATUS register
lsb: 0
reset_value: '0'
width: 1
- WAKEUP1_CLRST:
access: w
description: Writing a 1 to this bit clears the STATUS event bit 1 in the
STATUS register
lsb: 1
reset_value: '0'
width: 1
- WAKEUP2_CLRST:
access: w
description: Writing a 1 to this bit clears the STATUS event bit 2 in the
STATUS register
lsb: 2
reset_value: '0'
width: 1
- WAKEUP3_CLRST:
access: w
description: Writing a 1 to this bit clears the STATUS event bit 3 in the
STATUS register
lsb: 3
reset_value: '0'
width: 1
- ATIMER_CLRST:
access: w
description: Writing a 1 to this bit clears the STATUS event bit 4 in the
STATUS register
lsb: 4
reset_value: '0'
width: 1
- RTC_CLRST:
access: w
description: Writing a 1 to this bit clears the STATUS event bit 5 in the
STATUS register
lsb: 5
reset_value: '0'
width: 1
- BOD_CLRST:
access: w
description: Writing a 1 to this bit clears the STATUS event bit 6 in the
STATUS register
lsb: 6
reset_value: '0'
width: 1
- WWDT_CLRST:
access: w
description: Writing a 1 to this bit clears the STATUS event bit 7 in the
STATUS register
lsb: 7
reset_value: '0'
width: 1
- ETH_CLRST:
access: w
description: Writing a 1 to this bit clears the STATUS event bit 8 in the
STATUS register
lsb: 8
reset_value: '0'
width: 1
- USB0_CLRST:
access: w
description: Writing a 1 to this bit clears the STATUS event bit 9 in the
STATUS register
lsb: 9
reset_value: '0'
width: 1
- USB1_CLRST:
access: w
description: Writing a 1 to this bit clears the STATUS event bit 10 in the
STATUS register
lsb: 10
reset_value: '0'
width: 1
- SDMCC_CLRST:
access: w
description: Writing a 1 to this bit clears the STATUS event bit 11 in the
STATUS register
lsb: 11
reset_value: '0'
width: 1
- CAN_CLRST:
access: w
description: Writing a 1 to this bit clears the STATUS event bit 12 in the
STATUS register
lsb: 12
reset_value: '0'
width: 1
- TIM2_CLRST:
access: w
description: Writing a 1 to this bit clears the STATUS event bit 13 in the
STATUS register
lsb: 13
reset_value: '0'
width: 1
- TIM6_CLRST:
access: w
description: Writing a 1 to this bit clears the STATUS event bit 14 in the
STATUS register
lsb: 14
reset_value: '0'
width: 1
- QEI_CLRST:
access: w
description: Writing a 1 to this bit clears the STATUS event bit 15 in the
STATUS register
lsb: 15
reset_value: '0'
width: 1
- TIM14_CLRST:
access: w
description: Writing a 1 to this bit clears the STATUS event bit 16 in the
STATUS register
lsb: 16
reset_value: '0'
width: 1
- RESET_CLRST:
access: w
description: Writing a 1 to this bit clears the STATUS event bit 19 in the
STATUS register
lsb: 19
reset_value: '0'
width: 1
- EVENTROUTER_SET_STAT:
fields: !!omap
- WAKEUP0_SETST:
access: w
description: Writing a 1 to this bit sets the STATUS event bit 0 in the STATUS
register
lsb: 0
reset_value: '0'
width: 1
- WAKEUP1_SETST:
access: w
description: Writing a 1 to this bit sets the STATUS event bit 1 in the STATUS
register
lsb: 1
reset_value: '0'
width: 1
- WAKEUP2_SETST:
access: w
description: Writing a 1 to this bit sets the STATUS event bit 2 in the STATUS
register
lsb: 2
reset_value: '0'
width: 1
- WAKEUP3_SETST:
access: w
description: Writing a 1 to this bit sets the STATUS event bit 3 in the STATUS
register
lsb: 3
reset_value: '0'
width: 1
- ATIMER_SETST:
access: w
description: Writing a 1 to this bit sets the STATUS event bit 4 in the STATUS
register
lsb: 4
reset_value: '0'
width: 1
- RTC_SETST:
access: w
description: Writing a 1 to this bit sets the STATUS event bit 5 in the STATUS
register
lsb: 5
reset_value: '0'
width: 1
- BOD_SETST:
access: w
description: Writing a 1 to this bit sets the STATUS event bit 6 in the STATUS
register
lsb: 6
reset_value: '0'
width: 1
- WWDT_SETST:
access: w
description: Writing a 1 to this bit sets the STATUS event bit 7 in the STATUS
register
lsb: 7
reset_value: '0'
width: 1
- ETH_SETST:
access: w
description: Writing a 1 to this bit sets the STATUS event bit 8 in the STATUS
register
lsb: 8
reset_value: '0'
width: 1
- USB0_SETST:
access: w
description: Writing a 1 to this bit sets the STATUS event bit 9 in the STATUS
register
lsb: 9
reset_value: '0'
width: 1
- USB1_SETST:
access: w
description: Writing a 1 to this bit sets the STATUS event bit 10 in the STATUS
register
lsb: 10
reset_value: '0'
width: 1
- SDMCC_SETST:
access: w
description: Writing a 1 to this bit sets the STATUS event bit 11 in the STATUS
register
lsb: 11
reset_value: '0'
width: 1
- CAN_SETST:
access: w
description: Writing a 1 to this bit sets the STATUS event bit 12 in the STATUS
register
lsb: 12
reset_value: '0'
width: 1
- TIM2_SETST:
access: w
description: Writing a 1 to this bit sets the STATUS event bit 13 in the STATUS
register
lsb: 13
reset_value: '0'
width: 1
- TIM6_SETST:
access: w
description: Writing a 1 to this bit sets the STATUS event bit 14 in the STATUS
register
lsb: 14
reset_value: '0'
width: 1
- QEI_SETST:
access: w
description: Writing a 1 to this bit sets the STATUS event bit 15 in the STATUS
register
lsb: 15
reset_value: '0'
width: 1
- TIM14_SETST:
access: w
description: Writing a 1 to this bit sets the STATUS event bit 16 in the STATUS
register
lsb: 16
reset_value: '0'
width: 1
- RESET_SETST:
access: w
description: Writing a 1 to this bit sets the STATUS event bit 19 in the STATUS
register
lsb: 19
reset_value: '0'
width: 1

25
libopencm3/scripts/data/lpc43xx/gen.py Executable file
View File

@@ -0,0 +1,25 @@
#!/usr/bin/env python2
import sys
import yaml
registers = yaml.load(open(sys.argv[1], 'r'))
for register_name, register in registers.iteritems():
print('/* --- %s values %s */' % (register_name, '-' * (50 - len(register_name))))
print
fields = register['fields']
#for field_name, field in sorted(fields.items(), lambda x, y: cmp(x[1]['lsb'], y[1]['lsb'])):
for field_name, field in fields.items():
mask_bits = (1 << field['width']) - 1
print('/* %s: %s */' % (field_name, field['description']))
print('#define %s_%s_SHIFT (%d)' % (
register_name, field_name, field['lsb'],
))
print('#define %s_%s_MASK (0x%x << %s_%s_SHIFT)' % (
register_name, field_name, mask_bits, register_name, field_name,
))
print('#define %s_%s(x) ((x) << %s_%s_SHIFT)' % (
register_name, field_name, register_name, field_name,
))
print

961
libopencm3/scripts/data/lpc43xx/gima.yaml Normal file
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!!omap
- GIMA_CAP0_0_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_CAP0_1_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_CAP0_2_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_CAP0_3_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_CAP1_0_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_CAP1_1_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_CAP1_2_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_CAP1_3_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_CAP2_0_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_CAP2_1_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_CAP2_2_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_CAP2_3_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_CAP3_0_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_CAP3_1_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_CAP3_2_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_CAP3_3_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_CTIN_0_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_CTIN_1_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_CTIN_2_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_CTIN_3_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_CTIN_4_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_CTIN_5_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_CTIN_6_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_CTIN_7_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_VADC_TRIGGER_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_EVENTROUTER_13_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_EVENTROUTER_14_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_EVENTROUTER_16_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_ADCSTART0_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4
- GIMA_ADCSTART1_IN:
fields: !!omap
- INV:
access: rw
description: Invert input
lsb: 0
reset_value: '0'
width: 1
- EDGE:
access: rw
description: Enable rising edge detection
lsb: 1
reset_value: '0'
width: 1
- SYNCH:
access: rw
description: Enable synchronization
lsb: 2
reset_value: '0'
width: 1
- PULSE:
access: rw
description: Enable single pulse generation
lsb: 3
reset_value: '0'
width: 1
- SELECT:
access: rw
description: Select input
lsb: 4
reset_value: '0'
width: 4

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libopencm3/scripts/data/lpc43xx/gpdma.yaml Normal file
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4926
libopencm3/scripts/data/lpc43xx/gpio.yaml Normal file
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415
libopencm3/scripts/data/lpc43xx/i2c.yaml Normal file
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!!omap
- I2C0_CONSET:
fields: !!omap
- AA:
access: rw
description: Assert acknowledge flag
lsb: 2
reset_value: '0'
width: 1
- SI:
access: rw
description: I2C interrupt flag
lsb: 3
reset_value: '0'
width: 1
- STO:
access: rw
description: STOP flag
lsb: 4
reset_value: '0'
width: 1
- STA:
access: rw
description: START flag
lsb: 5
reset_value: '0'
width: 1
- I2EN:
access: rw
description: I2C interface enable
lsb: 6
reset_value: '0'
width: 1
- I2C1_CONSET:
fields: !!omap
- AA:
access: rw
description: Assert acknowledge flag
lsb: 2
reset_value: '0'
width: 1
- SI:
access: rw
description: I2C interrupt flag
lsb: 3
reset_value: '0'
width: 1
- STO:
access: rw
description: STOP flag
lsb: 4
reset_value: '0'
width: 1
- STA:
access: rw
description: START flag
lsb: 5
reset_value: '0'
width: 1
- I2EN:
access: rw
description: I2C interface enable
lsb: 6
reset_value: '0'
width: 1
- I2C0_STAT:
fields: !!omap
- STATUS:
access: r
description: These bits give the actual status information about the I2C interface
lsb: 3
reset_value: '0x1f'
width: 5
- I2C1_STAT:
fields: !!omap
- STATUS:
access: r
description: These bits give the actual status information about the I2C interface
lsb: 3
reset_value: '0x1f'
width: 5
- I2C0_DAT:
fields: !!omap
- DATA:
access: rw
description: This register holds data values that have been received or are
to be transmitted
lsb: 0
reset_value: '0'
width: 8
- I2C1_DAT:
fields: !!omap
- DATA:
access: rw
description: This register holds data values that have been received or are
to be transmitted
lsb: 0
reset_value: '0'
width: 8
- I2C0_ADR0:
fields: !!omap
- GC:
access: rw
description: General Call enable bit
lsb: 0
reset_value: '0'
width: 1
- ADDRESS:
access: rw
description: The I2C device address for slave mode
lsb: 1
reset_value: '0'
width: 7
- I2C1_ADR0:
fields: !!omap
- GC:
access: rw
description: General Call enable bit
lsb: 0
reset_value: '0'
width: 1
- ADDRESS:
access: rw
description: The I2C device address for slave mode
lsb: 1
reset_value: '0'
width: 7
- I2C0_SCLH:
fields: !!omap
- SCLH:
access: rw
description: Count for SCL HIGH time period selection
lsb: 0
reset_value: '0x0004'
width: 16
- I2C1_SCLH:
fields: !!omap
- SCLH:
access: rw
description: Count for SCL HIGH time period selection
lsb: 0
reset_value: '0x0004'
width: 16
- I2C0_SCLL:
fields: !!omap
- SCLL:
access: rw
description: Count for SCL LOW time period selection
lsb: 0
reset_value: '0x0004'
width: 16
- I2C1_SCLL:
fields: !!omap
- SCLL:
access: rw
description: Count for SCL LOW time period selection
lsb: 0
reset_value: '0x0004'
width: 16
- I2C0_CONCLR:
fields: !!omap
- AAC:
access: w
description: Assert acknowledge Clear bit
lsb: 2
reset_value: '0'
width: 1
- SIC:
access: w
description: I2C interrupt Clear bit
lsb: 3
reset_value: '0'
width: 1
- STAC:
access: w
description: START flag Clear bit
lsb: 5
reset_value: '0'
width: 1
- I2ENC:
access: w
description: I2C interface Disable bit
lsb: 6
reset_value: '0'
width: 1
- I2C1_CONCLR:
fields: !!omap
- AAC:
access: w
description: Assert acknowledge Clear bit
lsb: 2
reset_value: '0'
width: 1
- SIC:
access: w
description: I2C interrupt Clear bit
lsb: 3
reset_value: '0'
width: 1
- STAC:
access: w
description: START flag Clear bit
lsb: 5
reset_value: '0'
width: 1
- I2ENC:
access: w
description: I2C interface Disable bit
lsb: 6
reset_value: '0'
width: 1
- I2C0_MMCTRL:
fields: !!omap
- MM_ENA:
access: rw
description: Monitor mode enable
lsb: 0
reset_value: '0'
width: 1
- ENA_SCL:
access: rw
description: SCL output enable
lsb: 1
reset_value: '0'
width: 1
- MATCH_ALL:
access: rw
description: Select interrupt register match
lsb: 2
reset_value: '0'
width: 1
- I2C1_MMCTRL:
fields: !!omap
- MM_ENA:
access: rw
description: Monitor mode enable
lsb: 0
reset_value: '0'
width: 1
- ENA_SCL:
access: rw
description: SCL output enable
lsb: 1
reset_value: '0'
width: 1
- MATCH_ALL:
access: rw
description: Select interrupt register match
lsb: 2
reset_value: '0'
width: 1
- I2C0_ADR1:
fields: !!omap
- GC:
access: rw
description: General Call enable bit
lsb: 0
reset_value: '0'
width: 1
- ADDRESS:
access: rw
description: The I2C device address for slave mode
lsb: 1
reset_value: '0'
width: 7
- I2C1_ADR1:
fields: !!omap
- GC:
access: rw
description: General Call enable bit
lsb: 0
reset_value: '0'
width: 1
- ADDRESS:
access: rw
description: The I2C device address for slave mode
lsb: 1
reset_value: '0'
width: 7
- I2C0_ADR2:
fields: !!omap
- GC:
access: rw
description: General Call enable bit
lsb: 0
reset_value: '0'
width: 1
- ADDRESS:
access: rw
description: The I2C device address for slave mode
lsb: 1
reset_value: '0'
width: 7
- I2C1_ADR2:
fields: !!omap
- GC:
access: rw
description: General Call enable bit
lsb: 0
reset_value: '0'
width: 1
- ADDRESS:
access: rw
description: The I2C device address for slave mode
lsb: 1
reset_value: '0'
width: 7
- I2C0_ADR3:
fields: !!omap
- GC:
access: rw
description: General Call enable bit
lsb: 0
reset_value: '0'
width: 1
- ADDRESS:
access: rw
description: The I2C device address for slave mode
lsb: 1
reset_value: '0'
width: 7
- I2C1_ADR3:
fields: !!omap
- GC:
access: rw
description: General Call enable bit
lsb: 0
reset_value: '0'
width: 1
- ADDRESS:
access: rw
description: The I2C device address for slave mode
lsb: 1
reset_value: '0'
width: 7
- I2C0_DATA_BUFFER:
fields: !!omap
- DATA:
access: r
description: This register holds contents of the 8 MSBs of the DAT shift register
lsb: 0
reset_value: '0'
width: 8
- I2C1_DATA_BUFFER:
fields: !!omap
- DATA:
access: r
description: This register holds contents of the 8 MSBs of the DAT shift register
lsb: 0
reset_value: '0'
width: 8
- I2C0_MASK0:
fields: !!omap
- MASK:
access: rw
description: Mask bits
lsb: 1
reset_value: '0'
width: 7
- I2C1_MASK0:
fields: !!omap
- MASK:
access: rw
description: Mask bits
lsb: 1
reset_value: '0'
width: 7
- I2C0_MASK1:
fields: !!omap
- MASK:
access: rw
description: Mask bits
lsb: 1
reset_value: '0'
width: 7
- I2C1_MASK1:
fields: !!omap
- MASK:
access: rw
description: Mask bits
lsb: 1
reset_value: '0'
width: 7
- I2C0_MASK2:
fields: !!omap
- MASK:
access: rw
description: Mask bits
lsb: 1
reset_value: '0'
width: 7
- I2C1_MASK2:
fields: !!omap
- MASK:
access: rw
description: Mask bits
lsb: 1
reset_value: '0'
width: 7
- I2C0_MASK3:
fields: !!omap
- MASK:
access: rw
description: Mask bits
lsb: 1
reset_value: '0'
width: 7
- I2C1_MASK3:
fields: !!omap
- MASK:
access: rw
description: Mask bits
lsb: 1
reset_value: '0'
width: 7

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!!omap
- I2S0_DAO:
fields: !!omap
- WORDWIDTH:
access: rw
description: Selects the number of bytes in data
lsb: 0
reset_value: '1'
width: 2
- MONO:
access: rw
description: When 1, data is of monaural format. When 0, the data is in stereo
format
lsb: 2
reset_value: '0'
width: 1
- STOP:
access: rw
description: When 1, disables accesses on FIFOs, places the transmit channel
in mute mode
lsb: 3
reset_value: '0'
width: 1
- RESET:
access: rw
description: When 1, asynchronously resets the transmit channel and FIFO
lsb: 4
reset_value: '0'
width: 1
- WS_SEL:
access: rw
description: When 0, the interface is in master mode. When 1, the interface
is in slave mode
lsb: 5
reset_value: '1'
width: 1
- WS_HALFPERIOD:
access: rw
description: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod
= 31.
lsb: 6
reset_value: '0x1f'
width: 9
- MUTE:
access: rw
description: When 1, the transmit channel sends only zeroes
lsb: 15
reset_value: '1'
width: 1
- I2S1_DAO:
fields: !!omap
- WORDWIDTH:
access: rw
description: Selects the number of bytes in data
lsb: 0
reset_value: '1'
width: 2
- MONO:
access: rw
description: When 1, data is of monaural format. When 0, the data is in stereo
format
lsb: 2
reset_value: '0'
width: 1
- STOP:
access: rw
description: When 1, disables accesses on FIFOs, places the transmit channel
in mute mode
lsb: 3
reset_value: '0'
width: 1
- RESET:
access: rw
description: When 1, asynchronously resets the transmit channel and FIFO
lsb: 4
reset_value: '0'
width: 1
- WS_SEL:
access: rw
description: When 0, the interface is in master mode. When 1, the interface
is in slave mode
lsb: 5
reset_value: '1'
width: 1
- WS_HALFPERIOD:
access: rw
description: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod
= 31.
lsb: 6
reset_value: '0x1f'
width: 9
- MUTE:
access: rw
description: When 1, the transmit channel sends only zeroes
lsb: 15
reset_value: '1'
width: 1
- I2S0_DAI:
fields: !!omap
- WORDWIDTH:
access: rw
description: Selects the number of bytes in data
lsb: 0
reset_value: '1'
width: 2
- MONO:
access: rw
description: When 1, data is of monaural format. When 0, the data is in stereo
format
lsb: 2
reset_value: '0'
width: 1
- STOP:
access: rw
description: When 1, disables accesses on FIFOs, places the transmit channel
in mute mode
lsb: 3
reset_value: '0'
width: 1
- RESET:
access: rw
description: When 1, asynchronously resets the transmit channel and FIFO
lsb: 4
reset_value: '0'
width: 1
- WS_SEL:
access: rw
description: When 0, the interface is in master mode. When 1, the interface
is in slave mode
lsb: 5
reset_value: '1'
width: 1
- WS_HALFPERIOD:
access: rw
description: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod
= 31.
lsb: 6
reset_value: '0x1f'
width: 9
- MUTE:
access: rw
description: When 1, the transmit channel sends only zeroes
lsb: 15
reset_value: '1'
width: 1
- I2S1_DAI:
fields: !!omap
- WORDWIDTH:
access: rw
description: Selects the number of bytes in data
lsb: 0
reset_value: '1'
width: 2
- MONO:
access: rw
description: When 1, data is of monaural format. When 0, the data is in stereo
format
lsb: 2
reset_value: '0'
width: 1
- STOP:
access: rw
description: When 1, disables accesses on FIFOs, places the transmit channel
in mute mode
lsb: 3
reset_value: '0'
width: 1
- RESET:
access: rw
description: When 1, asynchronously resets the transmit channel and FIFO
lsb: 4
reset_value: '0'
width: 1
- WS_SEL:
access: rw
description: When 0, the interface is in master mode. When 1, the interface
is in slave mode
lsb: 5
reset_value: '1'
width: 1
- WS_HALFPERIOD:
access: rw
description: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod
= 31.
lsb: 6
reset_value: '0x1f'
width: 9
- MUTE:
access: rw
description: When 1, the transmit channel sends only zeroes
lsb: 15
reset_value: '1'
width: 1
- I2S0_TXFIFO:
fields: !!omap
- I2STXFIFO:
access: w
description: 8 x 32-bit transmit FIFO
lsb: 0
reset_value: '0'
width: 32
- I2S1_TXFIFO:
fields: !!omap
- I2STXFIFO:
access: w
description: 8 x 32-bit transmit FIFO
lsb: 0
reset_value: '0'
width: 32
- I2S0_RXFIFO:
fields: !!omap
- I2SRXFIFO:
access: r
description: 8 x 32-bit receive FIFO
lsb: 0
reset_value: '0'
width: 32
- I2S1_RXFIFO:
fields: !!omap
- I2SRXFIFO:
access: r
description: 8 x 32-bit receive FIFO
lsb: 0
reset_value: '0'
width: 32
- I2S0_STATE:
fields: !!omap
- IRQ:
access: r
description: This bit reflects the presence of Receive Interrupt or Transmit
Interrupt
lsb: 0
reset_value: '1'
width: 1
- DMAREQ1:
access: r
description: This bit reflects the presence of Receive or Transmit DMA Request
1
lsb: 1
reset_value: '1'
width: 1
- DMAREQ2:
access: r
description: This bit reflects the presence of Receive or Transmit DMA Request
2
lsb: 2
reset_value: '1'
width: 1
- RX_LEVEL:
access: r
description: Reflects the current level of the Receive FIFO
lsb: 8
reset_value: '0'
width: 4
- TX_LEVEL:
access: r
description: Reflects the current level of the Transmit FIFO
lsb: 16
reset_value: '0'
width: 4
- I2S1_STATE:
fields: !!omap
- IRQ:
access: r
description: This bit reflects the presence of Receive Interrupt or Transmit
Interrupt
lsb: 0
reset_value: '1'
width: 1
- DMAREQ1:
access: r
description: This bit reflects the presence of Receive or Transmit DMA Request
1
lsb: 1
reset_value: '1'
width: 1
- DMAREQ2:
access: r
description: This bit reflects the presence of Receive or Transmit DMA Request
2
lsb: 2
reset_value: '1'
width: 1
- RX_LEVEL:
access: r
description: Reflects the current level of the Receive FIFO
lsb: 8
reset_value: '0'
width: 4
- TX_LEVEL:
access: r
description: Reflects the current level of the Transmit FIFO
lsb: 16
reset_value: '0'
width: 4
- I2S0_DMA1:
fields: !!omap
- RX_DMA1_ENABLE:
access: rw
description: When 1, enables DMA1 for I2S receive
lsb: 0
reset_value: '0'
width: 1
- TX_DMA1_ENABLE:
access: rw
description: When 1, enables DMA1 for I2S transmit
lsb: 1
reset_value: '0'
width: 1
- RX_DEPTH_DMA1:
access: rw
description: Set the FIFO level that triggers a receive DMA request on DMA1
lsb: 8
reset_value: '0'
width: 4
- TX_DEPTH_DMA1:
access: rw
description: Set the FIFO level that triggers a transmit DMA request on DMA1
lsb: 16
reset_value: '0'
width: 4
- I2S1_DMA1:
fields: !!omap
- RX_DMA1_ENABLE:
access: rw
description: When 1, enables DMA1 for I2S receive
lsb: 0
reset_value: '0'
width: 1
- TX_DMA1_ENABLE:
access: rw
description: When 1, enables DMA1 for I2S transmit
lsb: 1
reset_value: '0'
width: 1
- RX_DEPTH_DMA1:
access: rw
description: Set the FIFO level that triggers a receive DMA request on DMA1
lsb: 8
reset_value: '0'
width: 4
- TX_DEPTH_DMA1:
access: rw
description: Set the FIFO level that triggers a transmit DMA request on DMA1
lsb: 16
reset_value: '0'
width: 4
- I2S0_DMA2:
fields: !!omap
- RX_DMA2_ENABLE:
access: rw
description: When 1, enables DMA2 for I2S receive
lsb: 0
reset_value: '0'
width: 1
- TX_DMA2_ENABLE:
access: rw
description: When 1, enables DMA2 for I2S transmit
lsb: 1
reset_value: '0'
width: 1
- RX_DEPTH_DMA2:
access: rw
description: Set the FIFO level that triggers a receive DMA request on DMA2
lsb: 8
reset_value: '0'
width: 4
- TX_DEPTH_DMA2:
access: rw
description: Set the FIFO level that triggers a transmit DMA request on DMA2
lsb: 16
reset_value: '0'
width: 4
- I2S1_DMA2:
fields: !!omap
- RX_DMA2_ENABLE:
access: rw
description: When 1, enables DMA2 for I2S receive
lsb: 0
reset_value: '0'
width: 1
- TX_DMA2_ENABLE:
access: rw
description: When 1, enables DMA2 for I2S transmit
lsb: 1
reset_value: '0'
width: 1
- RX_DEPTH_DMA2:
access: rw
description: Set the FIFO level that triggers a receive DMA request on DMA2
lsb: 8
reset_value: '0'
width: 4
- TX_DEPTH_DMA2:
access: rw
description: Set the FIFO level that triggers a transmit DMA request on DMA2
lsb: 16
reset_value: '0'
width: 4
- I2S0_IRQ:
fields: !!omap
- RX_IRQ_ENABLE:
access: rw
description: When 1, enables I2S receive interrupt
lsb: 0
reset_value: '0'
width: 1
- TX_IRQ_ENABLE:
access: rw
description: When 1, enables I2S transmit interrupt
lsb: 1
reset_value: '0'
width: 1
- RX_DEPTH_IRQ:
access: rw
description: Set the FIFO level on which to create an irq request.
lsb: 8
reset_value: '0'
width: 4
- TX_DEPTH_IRQ:
access: rw
description: Set the FIFO level on which to create an irq request.
lsb: 16
reset_value: '0'
width: 4
- I2S1_IRQ:
fields: !!omap
- RX_IRQ_ENABLE:
access: rw
description: When 1, enables I2S receive interrupt
lsb: 0
reset_value: '0'
width: 1
- TX_IRQ_ENABLE:
access: rw
description: When 1, enables I2S transmit interrupt
lsb: 1
reset_value: '0'
width: 1
- RX_DEPTH_IRQ:
access: rw
description: Set the FIFO level on which to create an irq request.
lsb: 8
reset_value: '0'
width: 4
- TX_DEPTH_IRQ:
access: rw
description: Set the FIFO level on which to create an irq request.
lsb: 16
reset_value: '0'
width: 4
- I2S0_TXRATE:
fields: !!omap
- Y_DIVIDER:
access: rw
description: I2S transmit MCLK rate denominator
lsb: 0
reset_value: '0'
width: 8
- X_DIVIDER:
access: rw
description: I2S transmit MCLK rate numerator
lsb: 8
reset_value: '0'
width: 8
- I2S1_TXRATE:
fields: !!omap
- Y_DIVIDER:
access: rw
description: I2S transmit MCLK rate denominator
lsb: 0
reset_value: '0'
width: 8
- X_DIVIDER:
access: rw
description: I2S transmit MCLK rate numerator
lsb: 8
reset_value: '0'
width: 8
- I2S0_RXRATE:
fields: !!omap
- Y_DIVIDER:
access: rw
description: I2S receive MCLK rate denominator
lsb: 0
reset_value: '0'
width: 8
- X_DIVIDER:
access: rw
description: I2S receive MCLK rate numerator
lsb: 8
reset_value: '0'
width: 8
- I2S1_RXRATE:
fields: !!omap
- Y_DIVIDER:
access: rw
description: I2S receive MCLK rate denominator
lsb: 0
reset_value: '0'
width: 8
- X_DIVIDER:
access: rw
description: I2S receive MCLK rate numerator
lsb: 8
reset_value: '0'
width: 8
- I2S0_TXBITRATE:
fields: !!omap
- TX_BITRATE:
access: rw
description: I2S transmit bit rate
lsb: 0
reset_value: '0'
width: 6
- I2S1_TXBITRATE:
fields: !!omap
- TX_BITRATE:
access: rw
description: I2S transmit bit rate
lsb: 0
reset_value: '0'
width: 6
- I2S0_RXBITRATE:
fields: !!omap
- RX_BITRATE:
access: rw
description: I2S receive bit rate
lsb: 0
reset_value: '0'
width: 6
- I2S1_RXBITRATE:
fields: !!omap
- RX_BITRATE:
access: rw
description: I2S receive bit rate
lsb: 0
reset_value: '0'
width: 6
- I2S0_TXMODE:
fields: !!omap
- TXCLKSEL:
access: rw
description: Clock source selection for the transmit bit clock divider
lsb: 0
reset_value: '0'
width: 2
- TX4PIN:
access: rw
description: Transmit 4-pin mode selection
lsb: 2
reset_value: '0'
width: 1
- TXMCENA:
access: rw
description: Enable for the TX_MCLK output
lsb: 3
reset_value: '0'
width: 1
- I2S1_TXMODE:
fields: !!omap
- TXCLKSEL:
access: rw
description: Clock source selection for the transmit bit clock divider
lsb: 0
reset_value: '0'
width: 2
- TX4PIN:
access: rw
description: Transmit 4-pin mode selection
lsb: 2
reset_value: '0'
width: 1
- TXMCENA:
access: rw
description: Enable for the TX_MCLK output
lsb: 3
reset_value: '0'
width: 1
- I2S0_RXMODE:
fields: !!omap
- RXCLKSEL:
access: rw
description: Clock source selection for the receive bit clock divider
lsb: 0
reset_value: '0'
width: 2
- RX4PIN:
access: rw
description: Receive 4-pin mode selection
lsb: 2
reset_value: '0'
width: 1
- RXMCENA:
access: rw
description: Enable for the RX_MCLK output
lsb: 3
reset_value: '0'
width: 1
- I2S1_RXMODE:
fields: !!omap
- RXCLKSEL:
access: rw
description: Clock source selection for the receive bit clock divider
lsb: 0
reset_value: '0'
width: 2
- RX4PIN:
access: rw
description: Receive 4-pin mode selection
lsb: 2
reset_value: '0'
width: 1
- RXMCENA:
access: rw
description: Enable for the RX_MCLK output
lsb: 3
reset_value: '0'
width: 1

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libopencm3/scripts/data/lpc43xx/rgu.yaml Normal file
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libopencm3/scripts/data/lpc43xx/ritimer.yaml Normal file
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!!omap
- RITIMER_COMPVAL:
fields: !!omap
- RICOMP:
access: rw
description: Compare register
lsb: 0
reset_value: '0xFFFFFFFF'
width: 32
- RITIMER_MASK:
fields: !!omap
- RIMASK:
access: rw
description: Mask register
lsb: 0
reset_value: '0'
width: 32
- RITIMER_CTRL:
fields: !!omap
- RITINT:
access: rw
description: Interrupt flag
lsb: 0
reset_value: '0'
width: 1
- RITENCLR:
access: rw
description: Timer enable clear
lsb: 1
reset_value: '0'
width: 1
- RITENBR:
access: rw
description: Timer enable for debug
lsb: 2
reset_value: '1'
width: 1
- RITEN:
access: rw
description: Timer enable
lsb: 3
reset_value: '1'
width: 1
- RITIMER_COUNTER:
fields: !!omap
- RICOUNTER:
access: rw
description: 32-bit up counter
lsb: 0
reset_value: '0'
width: 32

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libopencm3/scripts/data/lpc43xx/scu.yaml Normal file
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libopencm3/scripts/data/lpc43xx/sgpio.yaml Normal file
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!!omap
- SSP0_CR0:
fields: !!omap
- DSS:
access: rw
description: Data Size Select
lsb: 0
reset_value: '0'
width: 4
- FRF:
access: rw
description: Frame Format
lsb: 4
reset_value: '0'
width: 2
- CPOL:
access: rw
description: Clock Out Polarity
lsb: 6
reset_value: '0'
width: 1
- CPHA:
access: rw
description: Clock Out Phase
lsb: 7
reset_value: '0'
width: 1
- SCR:
access: rw
description: Serial Clock Rate
lsb: 8
reset_value: '0'
width: 8
- SSP1_CR0:
fields: !!omap
- DSS:
access: rw
description: Data Size Select
lsb: 0
reset_value: '0'
width: 4
- FRF:
access: rw
description: Frame Format
lsb: 4
reset_value: '0'
width: 2
- CPOL:
access: rw
description: Clock Out Polarity
lsb: 6
reset_value: '0'
width: 1
- CPHA:
access: rw
description: Clock Out Phase
lsb: 7
reset_value: '0'
width: 1
- SCR:
access: rw
description: Serial Clock Rate
lsb: 8
reset_value: '0'
width: 8
- SSP0_CR1:
fields: !!omap
- LBM:
access: rw
description: Loop Back Mode
lsb: 0
reset_value: '0'
width: 1
- SSE:
access: rw
description: SSP Enable
lsb: 1
reset_value: '0'
width: 1
- MS:
access: rw
description: Master/Slave Mode
lsb: 2
reset_value: '0'
width: 1
- SOD:
access: rw
description: Slave Output Disable
lsb: 3
reset_value: '0'
width: 1
- SSP1_CR1:
fields: !!omap
- SSE:
access: rw
description: SSP Enable
lsb: 1
reset_value: '0'
width: 1
- MS:
access: rw
description: Master/Slave Mode
lsb: 2
reset_value: '0'
width: 1
- SOD:
access: rw
description: Slave Output Disable
lsb: 3
reset_value: '0'
width: 1
- SSP0_DR:
fields: !!omap
- DATA:
access: rw
description: Software can write data to be transmitted to this register, and
read data that has been
lsb: 0
reset_value: '0'
width: 16
- SSP1_DR:
fields: !!omap
- DATA:
access: rw
description: Software can write data to be transmitted to this register, and
read data that has been
lsb: 0
reset_value: '0'
width: 16
- SSP0_SR:
fields: !!omap
- TFE:
access: r
description: Transmit FIFO Empty
lsb: 0
reset_value: '1'
width: 1
- TNF:
access: r
description: Transmit FIFO Not Full
lsb: 1
reset_value: '1'
width: 1
- RNE:
access: r
description: Receive FIFO Not Empty
lsb: 2
reset_value: '0'
width: 1
- RFF:
access: r
description: Receive FIFO Full
lsb: 3
reset_value: '0'
width: 1
- BSY:
access: r
description: Busy.
lsb: 4
reset_value: '0'
width: 1
- SSP1_SR:
fields: !!omap
- TFE:
access: r
description: Transmit FIFO Empty
lsb: 0
reset_value: '1'
width: 1
- TNF:
access: r
description: Transmit FIFO Not Full
lsb: 1
reset_value: '1'
width: 1
- RNE:
access: r
description: Receive FIFO Not Empty
lsb: 2
reset_value: '0'
width: 1
- RFF:
access: r
description: Receive FIFO Full
lsb: 3
reset_value: '0'
width: 1
- BSY:
access: r
description: Busy.
lsb: 4
reset_value: '0'
width: 1
- SSP0_CPSR:
fields: !!omap
- CPSDVSR:
access: rw
description: SSP Clock Prescale Register
lsb: 0
reset_value: '0'
width: 8
- SSP1_CPSR:
fields: !!omap
- CPSDVSR:
access: rw
description: SSP Clock Prescale Register
lsb: 0
reset_value: '0'
width: 8
- SSP0_IMSC:
fields: !!omap
- RORIM:
access: rw
description: Software should set this bit to enable interrupt when a Receive
Overrun occurs
lsb: 0
reset_value: '0'
width: 1
- RTIM:
access: rw
description: Software should set this bit to enable interrupt when a Receive
Time-out condition occurs
lsb: 1
reset_value: '0'
width: 1
- RXIM:
access: rw
description: Software should set this bit to enable interrupt when the Rx
FIFO is at least half full
lsb: 2
reset_value: '0'
width: 1
- TXIM:
access: rw
description: Software should set this bit to enable interrupt when the Tx
FIFO is at least half empty
lsb: 3
reset_value: '0'
width: 1
- SSP1_IMSC:
fields: !!omap
- RORIM:
access: rw
description: Software should set this bit to enable interrupt when a Receive
Overrun occurs
lsb: 0
reset_value: '0'
width: 1
- RTIM:
access: rw
description: Software should set this bit to enable interrupt when a Receive
Time-out condition occurs
lsb: 1
reset_value: '0'
width: 1
- RXIM:
access: rw
description: Software should set this bit to enable interrupt when the Rx
FIFO is at least half full
lsb: 2
reset_value: '0'
width: 1
- TXIM:
access: rw
description: Software should set this bit to enable interrupt when the Tx
FIFO is at least half empty
lsb: 3
reset_value: '0'
width: 1
- SSP0_RIS:
fields: !!omap
- RORRIS:
access: r
description: This bit is 1 if another frame was completely received while
the RxFIFO was full
lsb: 0
reset_value: '0'
width: 1
- RTRIS:
access: r
description: This bit is 1 if the Rx FIFO is not empty, and has not been read
for a time-out period
lsb: 1
reset_value: '0'
width: 1
- RXRIS:
access: r
description: This bit is 1 if the Rx FIFO is at least half full
lsb: 2
reset_value: '0'
width: 1
- TXRIS:
access: r
description: This bit is 1 if the Tx FIFO is at least half empty
lsb: 3
reset_value: '1'
width: 1
- SSP1_RIS:
fields: !!omap
- RORRIS:
access: r
description: This bit is 1 if another frame was completely received while
the RxFIFO was full
lsb: 0
reset_value: '0'
width: 1
- RTRIS:
access: r
description: This bit is 1 if the Rx FIFO is not empty, and has not been read
for a time-out period
lsb: 1
reset_value: '0'
width: 1
- RXRIS:
access: r
description: This bit is 1 if the Rx FIFO is at least half full
lsb: 2
reset_value: '0'
width: 1
- TXRIS:
access: r
description: This bit is 1 if the Tx FIFO is at least half empty
lsb: 3
reset_value: '1'
width: 1
- SSP0_MIS:
fields: !!omap
- RORMIS:
access: r
description: This bit is 1 if another frame was completely received while
the RxFIFO was full, and this interrupt is enabled
lsb: 0
reset_value: '0'
width: 1
- RTMIS:
access: r
description: This bit is 1 if the Rx FIFO is not empty, has not been read
for a time-out period, and this interrupt is enabled
lsb: 1
reset_value: '0'
width: 1
- RXMIS:
access: r
description: This bit is 1 if the Rx FIFO is at least half full, and this
interrupt is enabled
lsb: 2
reset_value: '0'
width: 1
- TXMIS:
access: r
description: This bit is 1 if the Tx FIFO is at least half empty, and this
interrupt is enabled
lsb: 3
reset_value: '0'
width: 1
- SSP1_MIS:
fields: !!omap
- RORMIS:
access: r
description: This bit is 1 if another frame was completely received while
the RxFIFO was full, and this interrupt is enabled
lsb: 0
reset_value: '0'
width: 1
- RTMIS:
access: r
description: This bit is 1 if the Rx FIFO is not empty, has not been read
for a time-out period, and this interrupt is enabled
lsb: 1
reset_value: '0'
width: 1
- RXMIS:
access: r
description: This bit is 1 if the Rx FIFO is at least half full, and this
interrupt is enabled
lsb: 2
reset_value: '0'
width: 1
- TXMIS:
access: r
description: This bit is 1 if the Tx FIFO is at least half empty, and this
interrupt is enabled
lsb: 3
reset_value: '0'
width: 1
- SSP0_ICR:
fields: !!omap
- RORIC:
access: w
description: Writing a 1 to this bit clears the 'frame was received when RxFIFO
was full' interrupt
lsb: 0
reset_value: ''
width: 1
- RTIC:
access: w
description: Writing a 1 to this bit clears the Rx FIFO was not empty and
has not been read for a time-out period interrupt
lsb: 1
reset_value: ''
width: 1
- SSP1_ICR:
fields: !!omap
- RORIC:
access: w
description: Writing a 1 to this bit clears the 'frame was received when RxFIFO
was full' interrupt
lsb: 0
reset_value: ''
width: 1
- RTIC:
access: w
description: Writing a 1 to this bit clears the Rx FIFO was not empty and
has not been read for a time-out period interrupt
lsb: 1
reset_value: ''
width: 1
- SSP0_DMACR:
fields: !!omap
- RXDMAE:
access: rw
description: Receive DMA Enable
lsb: 0
reset_value: '0'
width: 1
- TXDMAE:
access: rw
description: Transmit DMA Enable
lsb: 1
reset_value: '0'
width: 1
- SSP1_DMACR:
fields: !!omap
- RXDMAE:
access: rw
description: Receive DMA Enable
lsb: 0
reset_value: '0'
width: 1
- TXDMAE:
access: rw
description: Transmit DMA Enable
lsb: 1
reset_value: '0'
width: 1

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libopencm3/scripts/data/lpc43xx/usb.yaml Normal file
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81
libopencm3/scripts/data/lpc43xx/yaml_odict.py Normal file
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import yaml
from collections import OrderedDict
def construct_odict(load, node):
"""This is the same as SafeConstructor.construct_yaml_omap(),
except the data type is changed to OrderedDict() and setitem is
used instead of append in the loop.
>>> yaml.load('''
... !!omap
... - foo: bar
... - mumble: quux
... - baz: gorp
... ''')
OrderedDict([('foo', 'bar'), ('mumble', 'quux'), ('baz', 'gorp')])
>>> yaml.load('''!!omap [ foo: bar, mumble: quux, baz : gorp ]''')
OrderedDict([('foo', 'bar'), ('mumble', 'quux'), ('baz', 'gorp')])
"""
omap = OrderedDict()
yield omap
if not isinstance(node, yaml.SequenceNode):
raise yaml.constructor.ConstructorError(
"while constructing an ordered map",
node.start_mark,
"expected a sequence, but found %s" % node.id, node.start_mark
)
for subnode in node.value:
if not isinstance(subnode, yaml.MappingNode):
raise yaml.constructor.ConstructorError(
"while constructing an ordered map", node.start_mark,
"expected a mapping of length 1, but found %s" % subnode.id,
subnode.start_mark
)
if len(subnode.value) != 1:
raise yaml.constructor.ConstructorError(
"while constructing an ordered map", node.start_mark,
"expected a single mapping item, but found %d items" % len(subnode.value),
subnode.start_mark
)
key_node, value_node = subnode.value[0]
key = load.construct_object(key_node)
value = load.construct_object(value_node)
omap[key] = value
yaml.add_constructor(u'tag:yaml.org,2002:omap', construct_odict)
def repr_pairs(dump, tag, sequence, flow_style=None):
"""This is the same code as BaseRepresenter.represent_sequence(),
but the value passed to dump.represent_data() in the loop is a
dictionary instead of a tuple."""
value = []
node = yaml.SequenceNode(tag, value, flow_style=flow_style)
if dump.alias_key is not None:
dump.represented_objects[dump.alias_key] = node
best_style = True
for (key, val) in sequence:
item = dump.represent_data({key: val})
if not (isinstance(item, yaml.ScalarNode) and not item.style):
best_style = False
value.append(item)
if flow_style is None:
if dump.default_flow_style is not None:
node.flow_style = dump.default_flow_style
else:
node.flow_style = best_style
return node
def repr_odict(dumper, data):
"""
>>> data = OrderedDict([('foo', 'bar'), ('mumble', 'quux'), ('baz', 'gorp')])
>>> yaml.dump(data, default_flow_style=False)
'!!omap\\n- foo: bar\\n- mumble: quux\\n- baz: gorp\\n'
>>> yaml.dump(data, default_flow_style=True)
'!!omap [foo: bar, mumble: quux, baz: gorp]\\n'
"""
return repr_pairs(dumper, u'tag:yaml.org,2002:omap', data.iteritems())
yaml.add_representer(OrderedDict, repr_odict)