udpstream: PIXBLT L,XY blit primitive (vram.asm) and a 256 KB .bss

vram_blit_ copies a 1-bpp rectangle from RAM to VRAM.  The manual has no L,L
variant, so the destination is XY and the hardware forms the address:
  B0=SADDR  B1=SPTCH  B2=DADDR(XY)  B3=DPTCH=0x800  B4=OFFSET=0x04000000
  B7=DYDX   PSIZE=1  PMASK=0  CONVSP=CONVDP=0x14  CONTROL raster-op=0
SPTCH is a parameter because 0 makes every row read the same source address,
which is how one expanded row can be stamped eight times down the screen.

The .bss region in the linker command grows from 0x40000 to 0x200000 address
units (32 KB -> 256 KB) so a 1280x1024 1-bpp frame buffer (163840 B) fits; the
previous .coff had been built from sources that were not yet committed.

bench-sweep.sh gains its executable bit.

harness/udpstream/build-lance.sh

@@ -43,7 +43,7 @@ cp "$DIR/vram.asm" "$WORK/VRAM.ASM"
     printf '%s\n' 'MEMORY'
     printf '%s\n' '{'
     printf '%s\n' "  prog: origin = ${TEXT}h, length = 20000h"
-    printf '%s\n' "  ram:  origin = ${BSS}h,  length = 40000h"
+    printf '%s\n' "  ram:  origin = ${BSS}h,  length = 200000h"
     printf '%s\n' '}'
     printf '%s\n' 'SECTIONS'
     printf '%s\n' '{'

harness/udpstream/vram.asm

@@ -56,4 +56,57 @@ _vram_fill_:
 	move	*sp+, b2, 1
 	rets
 
+; vram_blit_ -- copy a 1-bpp rectangle from RAM to VRAM with PIXBLT L,XY.
+; The manual has no L,L variant; the destination is XY so the hardware forms
+; the address from OFFSET + y*CONVDP + x (rom:07ee9db6 does the same with
+; MOVI 0x4000000,B4).
+;
+;   _blit_src    linear source address (bit address, 1 bpp, SPTCH apart)
+;   _blit_sptch  source pitch in bits; 0 makes every row read the same address
+;   _blit_daddr  destination XY: (y << 16) | x
+;   _blit_dydx   dimensions XY: (rows << 16) | columns
+	.globl	_vram_blit_
+	.ref	_blit_src
+	.ref	_blit_sptch
+	.ref	_blit_daddr
+	.ref	_blit_dydx
+_vram_blit_:
+	setf	32, 0, 1
+	move	b0, -*sp, 1
+	move	b1, -*sp, 1
+	move	b2, -*sp, 1
+	move	b3, -*sp, 1
+	move	b4, -*sp, 1
+	move	b7, -*sp, 1
+
+	move	@_blit_src, b0, 1	; SADDR
+	move	@_blit_sptch, b1, 1	; SPTCH
+	move	@_blit_daddr, b2, 1	; DADDR (XY)
+	movi	800h, b3		; DPTCH = 256 bytes
+	movi	04000000h, b4		; OFFSET = VRAM base
+	move	@_blit_dydx, b7, 1	; DYDX (rows, columns)
+
+	movi	1, a1
+	move	a1, @0C0000150h, 0	; PSIZE = 1
+	movi	14h, a1
+	move	a1, @0C0000130h, 0	; CONVSP = pitch code for 0x800 bits
+	move	a1, @0C0000140h, 0	; CONVDP
+	clr	a1
+	move	a1, @0C0000160h, 0	; PMASK = 0
+	move	a1, @0C0000170h, 0
+	move	@0C00000B0h, a1, 0	; CONTROL: keep CD/RM/RR, raster op = 0
+	andi	0801Fh, a1
+	move	a1, @0C00000B0h, 0
+	move	@0C00000B0h, a1, 0	; read back (pipelined I/O)
+
+	pixblt	l, xy
+
+	move	*sp+, b7, 1
+	move	*sp+, b4, 1
+	move	*sp+, b3, 1
+	move	*sp+, b2, 1
+	move	*sp+, b1, 1
+	move	*sp+, b0, 1
+	rets
+
 	.end