mirror of
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mc68681: revert the TxRDY edit (REFUTED by the fitted part's datasheet); keep the overrun edit
Independent verification (reference/mc68681-datasheet-verification.md) read the SCN2681 spec: p.22 "Transmitter Disable Note" -- "TxRDY sets at the end of the 'start bit' time. It is during the start bit that the data in the transmit holding register is transferred to the transmit shift register." That is exactly upstream's tra_callback() assertion, so upstream was faithful and our edit contradicted the datasheet. Reverted; the revert note records the refutation and says not to re-apply. Commit 9902722165fc's "fix two DUART timing deviations" is therefore half false -- only the overrun edit stands. Reverting it does NOT relocate the failure: cfg2 (edit1 off, edit2 on) gives L3FA71BC0=0x00900040, L3FA753D0=3, L3FA767E0=0, L3FA6E4B0=6, console unchanged. "ISR one byte ahead" explained: TxRDY re-asserts at the end of the start bit (faithful), so the ISR writes the next byte ~1 bit into the current character, while MAME clocks the loopback receiver from the independent receive clock -- the datasheet (p.12, local loopback item 2) says "The transmit clock is used for the receiver". Edit 1 was masking that deviation. Next fix identified but not written (needs the quoted sentence read independently first, per process). Step-5 leads: crystal 3.6864 MHz is the datasheet nominal but the board crystal is still unconfirmed; CSRA=0x88 gives TX==RX==2400 baud (the rx arg is unused in calc_baud); MR1A=0x10 -> 5-bit frame matches the 0x1F mask; COUNTER_READY cleared (firmware's own Start-Counter read, not in IMR, not handled); INT1/INT2 immaterial (L3FA78D90 ignores the mask arg; OPCR/OPR cleared, so the single INTRN is the path). Regression holds.
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@@ -633,3 +633,101 @@ treated as a plain failure code until it is.
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* Console: `LEVEL1/2 TESTING **` then `LEVEL1/2 ERROR -> HOST PORT - 15` — **unchanged**.
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* Regression (no `VT1200_*`): `PC=3FDCE400 samples=199` — **holds**.
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---
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# CORRECTION — edit 1 (TxRDY) was REFUTED and has been REVERTED
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An independent worker read the fitted part's datasheet and checked both citations
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(`reference/mc68681-datasheet-verification.md`, commit `031d30da67dd`).
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* **Edit 1 (assert TxRDY at `tra_complete()` / the character boundary) — REFUTED.**
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Signetics SCN2681 p.22, "Transmitter Disable Note": *"TxRDY sets at the end of the
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'start bit' time. It is during the start bit that the data in the transmit holding
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register is transferred to the transmit shift register."* That is **exactly what
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upstream `tra_callback()` implemented**. The p.7 sentence the edit cited is real but
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says **nothing about when TxRDY is set**. So upstream was faithful and the edit was a
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datasheet-contradicting change that happened to line up one snapshot. It has been
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**reverted** (the note in `mc68681.cpp` now records the refutation and says not to
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re-apply it). The claim in commit `9902722165fc` — "fix two DUART timing deviations" —
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is therefore **half false**; only edit 2 stands.
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* **Edit 2 (latch overrun at the start bit) — CONFIRMED**, quote and application. Kept.
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* **FIFO depth faithful — CONFIRMED.** (My refutation of the owner's FIFO candidate also
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stands.)
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## Did reverting edit 1 relocate the failure to `L3FA71BC0`? No.
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Config 2 = edit 1 reverted, edit 2 kept:
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```
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L3FA71BC0 (rets 3FA753C0) = 0x00900040
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L3FA753D0 (rets 3FA767D0) = 0x00000003 (was 0x00000408 with edit 1)
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L3FA767E0 (rets 3FA77800) = 0
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L3FA6E4B0 (rets 3FA71BB0) = 6 (unchanged)
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console = 'LEVEL1/2 ERROR -> HOST PORT - 15' (unchanged)
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```
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Neither the console nor the caller's value changes; the failure did not relocate. It was
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never "in `L3FA71BC0`" — that came from the wrong-`rets` attribution corrected above.
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## The "ISR one byte ahead of the receiver" symptom — explained
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With faithful TxRDY (config 2), the last pass measures (cycles, `total_cycles()`):
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```
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THRA writes 44592939, 44598330, 44611350, 44629580, 44647808
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=> inter-write gap 5391, 13020, 18230, 18228 (char = 18226)
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SRA at each TxRDY 0C, 04, 04, 05, 05, 07
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=> index4 is NOT FFULL, index5 is NOT OVR
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```
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Cause: **TxRDY re-asserts at the end of the start bit (faithful), so the ISR writes the
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next byte ~1 bit into the current character** — i.e. the transmitter is ~1 byte ahead of
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the character boundary — while the loopback receiver only completes a character a full
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character after it was written. So the received count lags the transmit count, and the
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test's per-index snapshots (which expect lockstep) miss.
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The reason the receiver lags is **a real, independently-confirmed MAME deviation**: in
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local loopback the datasheet says (SCN2681 printed p.12, MR2A[7:6] = 10, item 2) *"The
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transmit clock is used for the receiver."* MAME instead clocks the loopback receiver from
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the **independent receive clock** (`set_rcv_rate` + the generic `m_rcv_clock` sampling
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with its half-cycle start guard). The confirmation is already recorded in
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`reference/mc68681-datasheet-verification.md` ("Incidental findings"): "MAME clocks the
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loopback receiver from the independent receive clock — directionally correct against the
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datasheet."
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So the story closes: edit 1 *masked* the loopback-clock deviation by dragging the
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transmitter back to the receiver; with faithful timing the deviation is exposed. **Edit 1
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must not be restored.** The next fix is to clock the loopback receiver from the transmit
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clock (SCN2681 p.12), which per the project's process needs the quoted sentence read
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independently before it is written.
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## The other step-5 leads
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* **DUART crystal.** `reference/duart-datasheet/SCN2681-transputer.txt` gives fCLK nominal
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3.6864 MHz ("the crystal oscillator operates directly from a 3.6864MHz clock"; Table 3
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is specified "Crystal or Clock = 3.6864MHz"), and `reference/keyboard-mouse/...` also
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shows a 3.6864 MHz part. That is the *datasheet's* nominal; **the VT1200 board crystal
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itself is still unconfirmed** (no schematic/guide figure). The driver's
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`XTAL(3'686'400)` therefore remains an assumption, but a well-founded one.
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* **CSRA-derived rates.** `CSRA = 0x88` -> `calc_baud(ch, false, 8)` and
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`calc_baud(ch, true, 8)`. In `duart_base_device::calc_baud` the `rx` argument is
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**unused** and both nibbles index the same `baud_rate_ACR_*` table, so TX and RX are
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both 2400 baud — **equal**. Not a mismatch. (Measured bit time ~415 us at 2400 baud
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confirms it.)
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* **Character frame.** `MR1A = 0x10` -> `recalc_framing` uses `(MR1 & 3) + 5` = **5 bits**,
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no parity, 1 stop; the test's pattern arithmetic masks with `0x1F`. Consistent.
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* **Counter lead — cleared.** `ISR` bit 0x08 is set by MAME's *Start Counter Command* read
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path (`case 0x0e`), and the firmware performs that read itself at boot. It is **not** in
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`IMR` (7) and `L3FA78D90` does not handle ISR bit 3, so it cannot disturb the test.
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* **INT1 vs INT2 — immaterial.** The two vector stubs differ only in their 3rd argument
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(2 / 4), and `L3FA78D90` **never reads that argument** (only `*a13(0xffc0)`/`0xffe0`).
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`OPCR` and `OPR` are written 0 on every transmit, so the discrete interrupt outputs
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(OP4/OP6) are not in use — the chip's single INTRN is the path, and the INT1 wiring is
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correct.
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## Acceptance / regression (current tree: edit 1 reverted, edit 2 kept)
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* Console: `'LEVEL1/2 TESTING ** '` then `'LEVEL1/2 ERROR -> HOST PORT - 15 '` — **still
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present**; no next gate.
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* Regression (no `VT1200_*`): `PC=3FDCE400 samples=199` — **holds**.
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@@ -0,0 +1,443 @@
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# win kind reg val pc -- every DUART access (not de-duplicated)
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1 W reg=D val=0000 pc=3F2000B0 cyc=7
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1 R reg=F val=00FF pc=3F200100 cyc=12
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1 W reg=F val=00FF pc=3F200100 cyc=12
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1 R reg=E val=00FF pc=3F200150 cyc=15
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1 W reg=E val=000F pc=3F200150 cyc=15
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1 R reg=F val=00FF pc=3F200250 cyc=29
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1 W reg=F val=0001 pc=3F200250 cyc=29
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1 R reg=D val=00F0 pc=3F200380 cyc=46
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1 R reg=D val=00F0 pc=3F200A20 cyc=2123
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1 R reg=D val=00F0 pc=3F202650 cyc=2715
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1 R reg=D val=00F0 pc=3F2045A0 cyc=465049
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1 R reg=E val=00FF pc=3F2042D0 cyc=576004
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1 W reg=E val=0001 pc=3F2042D0 cyc=576004
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1 R reg=D val=00F0 pc=3F204300 cyc=576005
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1 W reg=D val=0000 pc=3FDF1150 cyc=576167
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1 W reg=F val=0001 pc=3FDF1190 cyc=576171
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1 R reg=D val=00F0 pc=3FDF7DE0 cyc=1297177
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1 R reg=D val=00F0 pc=3F2045A0 cyc=1897379
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1 W reg=2 val=00CA pc=3FA90A00 cyc=3737622
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1 W reg=2 val=002A pc=3FA90AB0 cyc=3737945
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1 W reg=2 val=003A pc=3FA90B60 cyc=3738268
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1 W reg=2 val=004A pc=3FA90C10 cyc=3738591
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1 W reg=2 val=005A pc=3FA90CC0 cyc=3738914
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1 W reg=2 val=001A pc=3FA90D60 cyc=3739236
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1 W reg=A val=00CA pc=3FA90E10 cyc=3739559
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1 W reg=A val=002A pc=3FA90EC0 cyc=3739882
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1 W reg=A val=003A pc=3FA90F70 cyc=3740205
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1 W reg=A val=004A pc=3FA91020 cyc=3740528
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1 W reg=A val=005A pc=3FA910D0 cyc=3740851
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1 W reg=A val=001A pc=3FA91170 cyc=3741173
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1 W reg=F val=0080 pc=3FA7C330 cyc=3744820
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1 R reg=D val=00F0 pc=3F2045A0 cyc=10040220
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1 R reg=D val=00F0 pc=3F2045A0 cyc=15792800
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1 R reg=D val=00F0 pc=3F2045A0 cyc=15926711
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1 R reg=D val=00F0 pc=3F2045A0 cyc=34826663
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1 W reg=2 val=00FA pc=3FA778D0 cyc=43724635
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1 W reg=2 val=00CA pc=3FA77990 cyc=43724961
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1 W reg=2 val=002A pc=3FA77A30 cyc=43725282
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1 W reg=2 val=003A pc=3FA77AD0 cyc=43725603
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1 W reg=2 val=004A pc=3FA77B70 cyc=43725924
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1 W reg=2 val=005A pc=3FA77C10 cyc=43726245
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1 W reg=2 val=001A pc=3FA77CA0 cyc=43726565
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1 W reg=A val=00CA pc=3FA77990 cyc=43726956
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1 W reg=A val=002A pc=3FA77A30 cyc=43727277
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1 W reg=A val=003A pc=3FA77AD0 cyc=43727598
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1 W reg=A val=004A pc=3FA77B70 cyc=43727919
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1 W reg=A val=005A pc=3FA77C10 cyc=43728240
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1 W reg=A val=001A pc=3FA77CA0 cyc=43728560
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1 W reg=2 val=00FA pc=3FA778D0 cyc=43735282
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1 W reg=2 val=00CA pc=3FA77990 cyc=43735608
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1 W reg=2 val=002A pc=3FA77A30 cyc=43735929
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1 W reg=2 val=003A pc=3FA77AD0 cyc=43736250
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1 W reg=2 val=004A pc=3FA77B70 cyc=43736571
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1 W reg=2 val=005A pc=3FA77C10 cyc=43736892
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1 W reg=2 val=001A pc=3FA77CA0 cyc=43737212
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1 W reg=A val=00CA pc=3FA77990 cyc=43737603
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1 W reg=A val=002A pc=3FA77A30 cyc=43737924
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1 W reg=A val=003A pc=3FA77AD0 cyc=43738245
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1 W reg=A val=004A pc=3FA77B70 cyc=43738566
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1 W reg=A val=005A pc=3FA77C10 cyc=43738887
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1 W reg=A val=001A pc=3FA77CA0 cyc=43739207
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1 W reg=5 val=0007 pc=3FA78B40 cyc=43739320
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1 W reg=D val=0000 pc=3FA704E0 cyc=43739379
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1 W reg=4 val=0060 pc=3FA71CB0 cyc=43739476
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1 W reg=2 val=003A pc=3FA71F20 cyc=43739539
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1 W reg=2 val=002A pc=3FA71FD0 cyc=43739862
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1 W reg=2 val=004A pc=3FA72080 cyc=43740185
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1 W reg=2 val=001A pc=3FA72120 cyc=43740507
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1 W reg=1 val=0088 pc=3FA72220 cyc=43740837
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1 W reg=0 val=0012 pc=3FA73090 cyc=43745391
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1 W reg=0 val=0080 pc=3FA731B0 cyc=43745728
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1 W reg=2 val=0005 pc=3FA73260 cyc=43805849
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1 R reg=5 val=0009 pc=3FA78E30 cyc=43805931
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1 R reg=1 val=000C pc=3FA79E50 cyc=43806012
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1 W reg=3 val=00AA pc=3FA79F00 cyc=43806034
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1 R reg=1 val=0000 pc=3FA79FB0 cyc=43806056
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1 W reg=E val=0000 pc=3FA7A060 cyc=43806078
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1 W reg=F val=0000 pc=3FA7A110 cyc=43806100
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1 R reg=D val=00F0 pc=3FA7A1C0 cyc=43806122
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1 R reg=D val=00F0 pc=3FA7A320 cyc=43806156
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1 R reg=5 val=0009 pc=3FA78E30 cyc=43810019
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1 R reg=1 val=0004 pc=3FA79E50 cyc=43810100
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1 W reg=3 val=00FF pc=3FA79F00 cyc=43810122
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1 R reg=1 val=0000 pc=3FA79FB0 cyc=43810144
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1 W reg=E val=0000 pc=3FA7A060 cyc=43810166
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1 W reg=F val=0000 pc=3FA7A110 cyc=43810188
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1 R reg=D val=00F0 pc=3FA7A1C0 cyc=43810210
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1 R reg=D val=00F0 pc=3FA7A320 cyc=43810244
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1 R reg=5 val=0009 pc=3FA78E30 cyc=43828249
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1 R reg=1 val=0004 pc=3FA79E50 cyc=43828330
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1 W reg=3 val=00AA pc=3FA79F00 cyc=43828352
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1 R reg=1 val=0000 pc=3FA79FB0 cyc=43828374
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1 W reg=E val=0000 pc=3FA7A060 cyc=43828396
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1 W reg=F val=0000 pc=3FA7A110 cyc=43828418
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1 R reg=D val=00F0 pc=3FA7A1C0 cyc=43828440
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1 R reg=D val=00F0 pc=3FA7A320 cyc=43828474
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1 R reg=5 val=000A pc=3FA78E30 cyc=43829551
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1 R reg=1 val=0001 pc=3FA796D0 cyc=43829633
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1 R reg=3 val=002A pc=3FA79780 cyc=43829655
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1 R reg=1 val=0000 pc=3FA79830 cyc=43829677
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1 R reg=D val=00F0 pc=3FA798E0 cyc=43829699
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1 R reg=D val=00F0 pc=3FA79A20 cyc=43829733
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1 R reg=5 val=0009 pc=3FA78E30 cyc=43851686
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1 R reg=1 val=0004 pc=3FA79E50 cyc=43851767
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1 W reg=3 val=0055 pc=3FA79F00 cyc=43851789
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1 R reg=1 val=0000 pc=3FA79FB0 cyc=43851811
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1 W reg=E val=0000 pc=3FA7A060 cyc=43851833
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1 W reg=F val=0000 pc=3FA7A110 cyc=43851855
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1 R reg=D val=00F0 pc=3FA7A1C0 cyc=43851877
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1 R reg=D val=00F0 pc=3FA7A320 cyc=43851911
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1 R reg=5 val=000A pc=3FA78E30 cyc=43852988
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1 R reg=1 val=0001 pc=3FA796D0 cyc=43853070
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1 R reg=3 val=007F pc=3FA79780 cyc=43853092
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1 R reg=1 val=0000 pc=3FA79830 cyc=43853114
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1 R reg=D val=00F0 pc=3FA798E0 cyc=43853136
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1 R reg=D val=00F0 pc=3FA79A20 cyc=43853170
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1 R reg=5 val=0009 pc=3FA78E30 cyc=43875123
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1 R reg=1 val=0004 pc=3FA79E50 cyc=43875204
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1 W reg=3 val=0000 pc=3FA79F00 cyc=43875226
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1 R reg=1 val=0000 pc=3FA79FB0 cyc=43875248
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1 W reg=E val=0000 pc=3FA7A060 cyc=43875270
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1 W reg=F val=0000 pc=3FA7A110 cyc=43875292
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1 R reg=D val=00F0 pc=3FA7A1C0 cyc=43875314
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1 R reg=D val=00F0 pc=3FA7A320 cyc=43875348
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1 R reg=5 val=000A pc=3FA78E30 cyc=43876425
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1 R reg=1 val=0001 pc=3FA796D0 cyc=43876507
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1 R reg=3 val=002A pc=3FA79780 cyc=43876529
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1 R reg=1 val=0000 pc=3FA79830 cyc=43876551
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1 R reg=D val=00F0 pc=3FA798E0 cyc=43876573
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1 R reg=D val=00F0 pc=3FA79A20 cyc=43876607
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1 R reg=5 val=0009 pc=3FA78E30 cyc=43898560
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1 R reg=1 val=0004 pc=3FA7A3C0 cyc=43898630
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1 W reg=2 val=0008 pc=3FA7A3F0 cyc=43898636
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1 R reg=1 val=0000 pc=3FA7A440 cyc=43898644
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1 R reg=5 val=000A pc=3FA78E30 cyc=43899863
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1 R reg=1 val=0001 pc=3FA796D0 cyc=43899945
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1 R reg=3 val=0055 pc=3FA79780 cyc=43899967
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1 R reg=1 val=0000 pc=3FA79830 cyc=43899989
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1 R reg=D val=00F0 pc=3FA798E0 cyc=43900011
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1 R reg=D val=00F0 pc=3FA79A20 cyc=43900045
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1 R reg=5 val=000A pc=3FA78E30 cyc=43923301
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1 R reg=1 val=0009 pc=3FA796D0 cyc=43923383
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1 R reg=3 val=0000 pc=3FA79780 cyc=43923405
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1 R reg=1 val=0008 pc=3FA79830 cyc=43923427
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1 R reg=D val=00F0 pc=3FA798E0 cyc=43923449
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1 R reg=D val=00F0 pc=3FA79A20 cyc=43923483
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1 W reg=2 val=000A pc=3FA73420 cyc=43931657
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1 W reg=2 val=002A pc=3FA74BE0 cyc=43933007
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1 W reg=2 val=002B pc=3FA74C80 cyc=43933329
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1 W reg=2 val=004A pc=3FA74D10 cyc=43933650
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1 W reg=2 val=0065 pc=3FA74DA0 cyc=43933971
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1 R reg=5 val=000F pc=3FA78E30 cyc=43934053
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1 R reg=1 val=008D pc=3FA78FD0 cyc=43934094
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1 W reg=2 val=0055 pc=3FA79010 cyc=43934101
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1 W reg=2 val=0075 pc=3FA790C0 cyc=43934424
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1 R reg=1 val=008D pc=3FA79AE0 cyc=43934494
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1 R reg=3 val=0000 pc=3FA79B00 cyc=43934499
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1 W reg=2 val=0002 pc=3FA79B60 cyc=43934508
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1 R reg=1 val=000C pc=3FA79BB0 cyc=43934516
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1 R reg=5 val=000D pc=3FA78E30 cyc=43934741
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1 W reg=2 val=005A pc=3FA79110 cyc=43934780
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1 W reg=2 val=007A pc=3FA74E60 cyc=43995061
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||||
1 W reg=2 val=0050 pc=3FA74F10 cyc=43995384
|
||||
1 W reg=2 val=003A pc=3FA71F20 cyc=43995432
|
||||
1 W reg=2 val=002A pc=3FA71FD0 cyc=43995755
|
||||
1 W reg=2 val=004A pc=3FA72080 cyc=43996078
|
||||
1 W reg=2 val=001A pc=3FA72120 cyc=43996400
|
||||
1 W reg=1 val=0088 pc=3FA72220 cyc=43996730
|
||||
1 W reg=0 val=0013 pc=3FA73090 cyc=44001284
|
||||
1 W reg=0 val=0080 pc=3FA731B0 cyc=44001621
|
||||
1 W reg=2 val=0005 pc=3FA73260 cyc=44061742
|
||||
1 R reg=5 val=0009 pc=3FA78E30 cyc=44061824
|
||||
1 R reg=1 val=000C pc=3FA79E50 cyc=44061905
|
||||
1 W reg=3 val=00AA pc=3FA79F00 cyc=44061927
|
||||
1 R reg=1 val=0000 pc=3FA79FB0 cyc=44061949
|
||||
1 W reg=E val=0000 pc=3FA7A060 cyc=44061971
|
||||
1 W reg=F val=0000 pc=3FA7A110 cyc=44061993
|
||||
1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44062015
|
||||
1 R reg=D val=00F0 pc=3FA7A320 cyc=44062049
|
||||
1 R reg=5 val=0009 pc=3FA78E30 cyc=44067214
|
||||
1 R reg=1 val=0004 pc=3FA79E50 cyc=44067295
|
||||
1 W reg=3 val=00FF pc=3FA79F00 cyc=44067317
|
||||
1 R reg=1 val=0000 pc=3FA79FB0 cyc=44067339
|
||||
1 W reg=E val=0000 pc=3FA7A060 cyc=44067361
|
||||
1 W reg=F val=0000 pc=3FA7A110 cyc=44067383
|
||||
1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44067405
|
||||
1 R reg=D val=00F0 pc=3FA7A320 cyc=44067439
|
||||
1 R reg=5 val=0009 pc=3FA78E30 cyc=44088048
|
||||
1 R reg=1 val=0004 pc=3FA79E50 cyc=44088129
|
||||
1 W reg=3 val=00AA pc=3FA79F00 cyc=44088151
|
||||
1 R reg=1 val=0000 pc=3FA79FB0 cyc=44088173
|
||||
1 W reg=E val=0000 pc=3FA7A060 cyc=44088195
|
||||
1 W reg=F val=0000 pc=3FA7A110 cyc=44088217
|
||||
1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44088239
|
||||
1 R reg=D val=00F0 pc=3FA7A320 cyc=44088273
|
||||
1 R reg=5 val=000A pc=3FA78E30 cyc=44089350
|
||||
1 R reg=1 val=0001 pc=3FA796D0 cyc=44089432
|
||||
1 R reg=3 val=00AA pc=3FA79780 cyc=44089454
|
||||
1 R reg=1 val=0000 pc=3FA79830 cyc=44089476
|
||||
1 R reg=D val=00F0 pc=3FA798E0 cyc=44089498
|
||||
1 R reg=D val=00F0 pc=3FA79A20 cyc=44089532
|
||||
1 R reg=5 val=0009 pc=3FA78E30 cyc=44114090
|
||||
1 R reg=1 val=0004 pc=3FA79E50 cyc=44114171
|
||||
1 W reg=3 val=0055 pc=3FA79F00 cyc=44114193
|
||||
1 R reg=1 val=0000 pc=3FA79FB0 cyc=44114215
|
||||
1 W reg=E val=0000 pc=3FA7A060 cyc=44114237
|
||||
1 W reg=F val=0000 pc=3FA7A110 cyc=44114259
|
||||
1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44114281
|
||||
1 R reg=D val=00F0 pc=3FA7A320 cyc=44114315
|
||||
1 R reg=5 val=000A pc=3FA78E30 cyc=44115392
|
||||
1 R reg=1 val=0001 pc=3FA796D0 cyc=44115474
|
||||
1 R reg=3 val=00FF pc=3FA79780 cyc=44115496
|
||||
1 R reg=1 val=0000 pc=3FA79830 cyc=44115518
|
||||
1 R reg=D val=00F0 pc=3FA798E0 cyc=44115540
|
||||
1 R reg=D val=00F0 pc=3FA79A20 cyc=44115574
|
||||
1 R reg=5 val=0009 pc=3FA78E30 cyc=44140131
|
||||
1 R reg=1 val=0004 pc=3FA79E50 cyc=44140212
|
||||
1 W reg=3 val=0000 pc=3FA79F00 cyc=44140234
|
||||
1 R reg=1 val=0000 pc=3FA79FB0 cyc=44140256
|
||||
1 W reg=E val=0000 pc=3FA7A060 cyc=44140278
|
||||
1 W reg=F val=0000 pc=3FA7A110 cyc=44140300
|
||||
1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44140322
|
||||
1 R reg=D val=00F0 pc=3FA7A320 cyc=44140356
|
||||
1 R reg=5 val=000A pc=3FA78E30 cyc=44141433
|
||||
1 R reg=1 val=0001 pc=3FA796D0 cyc=44141515
|
||||
1 R reg=3 val=00AA pc=3FA79780 cyc=44141537
|
||||
1 R reg=1 val=0000 pc=3FA79830 cyc=44141559
|
||||
1 R reg=D val=00F0 pc=3FA798E0 cyc=44141581
|
||||
1 R reg=D val=00F0 pc=3FA79A20 cyc=44141615
|
||||
1 R reg=5 val=0009 pc=3FA78E30 cyc=44166172
|
||||
1 R reg=1 val=0004 pc=3FA7A3C0 cyc=44166242
|
||||
1 W reg=2 val=0008 pc=3FA7A3F0 cyc=44166248
|
||||
1 R reg=1 val=0000 pc=3FA7A440 cyc=44166256
|
||||
1 R reg=5 val=000A pc=3FA78E30 cyc=44167474
|
||||
1 R reg=1 val=0001 pc=3FA796D0 cyc=44167556
|
||||
1 R reg=3 val=0055 pc=3FA79780 cyc=44167578
|
||||
1 R reg=1 val=0000 pc=3FA79830 cyc=44167600
|
||||
1 R reg=D val=00F0 pc=3FA798E0 cyc=44167622
|
||||
1 R reg=D val=00F0 pc=3FA79A20 cyc=44167656
|
||||
1 R reg=5 val=000A pc=3FA78E30 cyc=44193517
|
||||
1 R reg=1 val=0009 pc=3FA796D0 cyc=44193599
|
||||
1 R reg=3 val=0000 pc=3FA79780 cyc=44193621
|
||||
1 R reg=1 val=0008 pc=3FA79830 cyc=44193643
|
||||
1 R reg=D val=00F0 pc=3FA798E0 cyc=44193665
|
||||
1 R reg=D val=00F0 pc=3FA79A20 cyc=44193699
|
||||
1 W reg=2 val=000A pc=3FA73420 cyc=44197687
|
||||
1 W reg=2 val=002A pc=3FA74BE0 cyc=44199037
|
||||
1 W reg=2 val=002B pc=3FA74C80 cyc=44199359
|
||||
1 W reg=2 val=004A pc=3FA74D10 cyc=44199680
|
||||
1 W reg=2 val=0065 pc=3FA74DA0 cyc=44200001
|
||||
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|
||||
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|
||||
1 W reg=2 val=0055 pc=3FA79010 cyc=44200131
|
||||
1 W reg=2 val=0075 pc=3FA790C0 cyc=44200454
|
||||
1 R reg=1 val=008D pc=3FA79AE0 cyc=44200524
|
||||
1 R reg=3 val=0000 pc=3FA79B00 cyc=44200529
|
||||
1 W reg=2 val=0002 pc=3FA79B60 cyc=44200538
|
||||
1 R reg=1 val=000C pc=3FA79BB0 cyc=44200546
|
||||
1 R reg=5 val=000D pc=3FA78E30 cyc=44200771
|
||||
1 W reg=2 val=005A pc=3FA79110 cyc=44200810
|
||||
1 W reg=2 val=007A pc=3FA74E60 cyc=44261091
|
||||
1 W reg=2 val=0050 pc=3FA74F10 cyc=44261414
|
||||
1 W reg=2 val=003A pc=3FA71F20 cyc=44261487
|
||||
1 W reg=2 val=002A pc=3FA71FD0 cyc=44261810
|
||||
1 W reg=2 val=004A pc=3FA72080 cyc=44262133
|
||||
1 W reg=2 val=001A pc=3FA72120 cyc=44262455
|
||||
1 W reg=1 val=0088 pc=3FA72220 cyc=44262785
|
||||
1 W reg=0 val=0002 pc=3FA73090 cyc=44267339
|
||||
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|
||||
1 W reg=2 val=0005 pc=3FA73260 cyc=44327797
|
||||
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|
||||
1 R reg=1 val=000C pc=3FA79E50 cyc=44327960
|
||||
1 W reg=3 val=00AA pc=3FA79F00 cyc=44327982
|
||||
1 R reg=1 val=0000 pc=3FA79FB0 cyc=44328004
|
||||
1 W reg=E val=0000 pc=3FA7A060 cyc=44328026
|
||||
1 W reg=F val=0000 pc=3FA7A110 cyc=44328048
|
||||
1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44328070
|
||||
1 R reg=D val=00F0 pc=3FA7A320 cyc=44328104
|
||||
1 R reg=5 val=0009 pc=3FA78E30 cyc=44333269
|
||||
1 R reg=1 val=0004 pc=3FA79E50 cyc=44333350
|
||||
1 W reg=3 val=00FF pc=3FA79F00 cyc=44333372
|
||||
1 R reg=1 val=0000 pc=3FA79FB0 cyc=44333394
|
||||
1 W reg=E val=0000 pc=3FA7A060 cyc=44333416
|
||||
1 W reg=F val=0000 pc=3FA7A110 cyc=44333438
|
||||
1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44333460
|
||||
1 R reg=D val=00F0 pc=3FA7A320 cyc=44333494
|
||||
1 R reg=5 val=0009 pc=3FA78E30 cyc=44354103
|
||||
1 R reg=1 val=0004 pc=3FA79E50 cyc=44354184
|
||||
1 W reg=3 val=00AA pc=3FA79F00 cyc=44354206
|
||||
1 R reg=1 val=0000 pc=3FA79FB0 cyc=44354228
|
||||
1 W reg=E val=0000 pc=3FA7A060 cyc=44354250
|
||||
1 W reg=F val=0000 pc=3FA7A110 cyc=44354272
|
||||
1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44354294
|
||||
1 R reg=D val=00F0 pc=3FA7A320 cyc=44354328
|
||||
1 R reg=5 val=000A pc=3FA78E30 cyc=44355405
|
||||
1 R reg=1 val=0021 pc=3FA796D0 cyc=44355487
|
||||
1 R reg=3 val=002A pc=3FA79780 cyc=44355509
|
||||
1 R reg=1 val=0000 pc=3FA79830 cyc=44355531
|
||||
1 R reg=D val=00F0 pc=3FA798E0 cyc=44355553
|
||||
1 R reg=D val=00F0 pc=3FA79A20 cyc=44355587
|
||||
1 R reg=5 val=0009 pc=3FA78E30 cyc=44380145
|
||||
1 R reg=1 val=0004 pc=3FA79E50 cyc=44380226
|
||||
1 W reg=3 val=0055 pc=3FA79F00 cyc=44380248
|
||||
1 R reg=1 val=0000 pc=3FA79FB0 cyc=44380270
|
||||
1 W reg=E val=0000 pc=3FA7A060 cyc=44380292
|
||||
1 W reg=F val=0000 pc=3FA7A110 cyc=44380314
|
||||
1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44380336
|
||||
1 R reg=D val=00F0 pc=3FA7A320 cyc=44380370
|
||||
1 R reg=5 val=000A pc=3FA78E30 cyc=44381447
|
||||
1 R reg=1 val=0021 pc=3FA796D0 cyc=44381529
|
||||
1 R reg=3 val=007F pc=3FA79780 cyc=44381551
|
||||
1 R reg=1 val=0000 pc=3FA79830 cyc=44381573
|
||||
1 R reg=D val=00F0 pc=3FA798E0 cyc=44381595
|
||||
1 R reg=D val=00F0 pc=3FA79A20 cyc=44381629
|
||||
1 R reg=5 val=0009 pc=3FA78E30 cyc=44406186
|
||||
1 R reg=1 val=0004 pc=3FA79E50 cyc=44406267
|
||||
1 W reg=3 val=0000 pc=3FA79F00 cyc=44406289
|
||||
1 R reg=1 val=0000 pc=3FA79FB0 cyc=44406311
|
||||
1 W reg=E val=0000 pc=3FA7A060 cyc=44406333
|
||||
1 W reg=F val=0000 pc=3FA7A110 cyc=44406355
|
||||
1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44406377
|
||||
1 R reg=D val=00F0 pc=3FA7A320 cyc=44406411
|
||||
1 R reg=5 val=000A pc=3FA78E30 cyc=44407488
|
||||
1 R reg=1 val=0021 pc=3FA796D0 cyc=44407570
|
||||
1 R reg=3 val=002A pc=3FA79780 cyc=44407592
|
||||
1 R reg=1 val=0000 pc=3FA79830 cyc=44407614
|
||||
1 R reg=D val=00F0 pc=3FA798E0 cyc=44407636
|
||||
1 R reg=D val=00F0 pc=3FA79A20 cyc=44407670
|
||||
1 R reg=5 val=0009 pc=3FA78E30 cyc=44432227
|
||||
1 R reg=1 val=0004 pc=3FA7A3C0 cyc=44432297
|
||||
1 W reg=2 val=0008 pc=3FA7A3F0 cyc=44432303
|
||||
1 R reg=1 val=0000 pc=3FA7A440 cyc=44432311
|
||||
1 R reg=5 val=000A pc=3FA78E30 cyc=44433529
|
||||
1 R reg=1 val=0001 pc=3FA796D0 cyc=44433611
|
||||
1 R reg=3 val=0055 pc=3FA79780 cyc=44433633
|
||||
1 R reg=1 val=0000 pc=3FA79830 cyc=44433655
|
||||
1 R reg=D val=00F0 pc=3FA798E0 cyc=44433677
|
||||
1 R reg=D val=00F0 pc=3FA79A20 cyc=44433711
|
||||
1 R reg=5 val=000A pc=3FA78E30 cyc=44459572
|
||||
1 R reg=1 val=0009 pc=3FA796D0 cyc=44459654
|
||||
1 R reg=3 val=0000 pc=3FA79780 cyc=44459676
|
||||
1 R reg=1 val=0008 pc=3FA79830 cyc=44459698
|
||||
1 R reg=D val=00F0 pc=3FA798E0 cyc=44459720
|
||||
1 R reg=D val=00F0 pc=3FA79A20 cyc=44459754
|
||||
1 W reg=2 val=000A pc=3FA73420 cyc=44463742
|
||||
1 W reg=2 val=002A pc=3FA74BE0 cyc=44465104
|
||||
1 W reg=2 val=002B pc=3FA74C80 cyc=44465426
|
||||
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|
||||
1 W reg=2 val=0065 pc=3FA74DA0 cyc=44466068
|
||||
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|
||||
1 R reg=1 val=008D pc=3FA78FD0 cyc=44466191
|
||||
1 W reg=2 val=0055 pc=3FA79010 cyc=44466198
|
||||
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|
||||
1 R reg=1 val=008D pc=3FA79AE0 cyc=44466591
|
||||
1 R reg=3 val=0000 pc=3FA79B00 cyc=44466596
|
||||
1 W reg=2 val=0002 pc=3FA79B60 cyc=44466605
|
||||
1 R reg=1 val=000C pc=3FA79BB0 cyc=44466613
|
||||
1 R reg=5 val=000D pc=3FA78E30 cyc=44466838
|
||||
1 W reg=2 val=005A pc=3FA79110 cyc=44466877
|
||||
1 W reg=2 val=007A pc=3FA74E60 cyc=44527158
|
||||
1 W reg=2 val=0050 pc=3FA74F10 cyc=44527481
|
||||
1 W reg=5 val=0000 pc=3FA78D10 cyc=44527649
|
||||
1 W reg=5 val=0001 pc=3FA78B40 cyc=44527781
|
||||
1 W reg=2 val=003A pc=3FA75570 cyc=44527906
|
||||
1 W reg=2 val=002A pc=3FA75620 cyc=44528229
|
||||
1 W reg=2 val=004A pc=3FA756D0 cyc=44528552
|
||||
1 W reg=2 val=001A pc=3FA75770 cyc=44528874
|
||||
1 W reg=1 val=0088 pc=3FA75870 cyc=44529204
|
||||
1 W reg=0 val=0010 pc=3FA75BC0 cyc=44532296
|
||||
1 W reg=0 val=0080 pc=3FA75CE0 cyc=44532633
|
||||
1 W reg=2 val=0005 pc=3FA75D90 cyc=44592754
|
||||
1 R reg=5 val=0009 pc=3FA78E30 cyc=44592836
|
||||
1 R reg=1 val=000C pc=3FA79E50 cyc=44592917
|
||||
1 W reg=3 val=00AA pc=3FA79F00 cyc=44592939
|
||||
1 R reg=1 val=0000 pc=3FA79FB0 cyc=44592961
|
||||
1 W reg=E val=0000 pc=3FA7A060 cyc=44592983
|
||||
1 W reg=F val=0000 pc=3FA7A110 cyc=44593005
|
||||
1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44593027
|
||||
1 R reg=D val=00F0 pc=3FA7A320 cyc=44593061
|
||||
1 R reg=5 val=0009 pc=3FA78E30 cyc=44598227
|
||||
1 R reg=1 val=0004 pc=3FA79E50 cyc=44598308
|
||||
1 W reg=3 val=00FF pc=3FA79F00 cyc=44598330
|
||||
1 R reg=1 val=0000 pc=3FA79FB0 cyc=44598352
|
||||
1 W reg=E val=0000 pc=3FA7A060 cyc=44598374
|
||||
1 W reg=F val=0000 pc=3FA7A110 cyc=44598396
|
||||
1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44598418
|
||||
1 R reg=D val=00F0 pc=3FA7A320 cyc=44598452
|
||||
1 R reg=5 val=0009 pc=3FA78E30 cyc=44611247
|
||||
1 R reg=1 val=0004 pc=3FA79E50 cyc=44611328
|
||||
1 W reg=3 val=00AA pc=3FA79F00 cyc=44611350
|
||||
1 R reg=1 val=0000 pc=3FA79FB0 cyc=44611372
|
||||
1 W reg=E val=0000 pc=3FA7A060 cyc=44611394
|
||||
1 W reg=F val=0000 pc=3FA7A110 cyc=44611416
|
||||
1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44611438
|
||||
1 R reg=D val=00F0 pc=3FA7A320 cyc=44611472
|
||||
1 R reg=5 val=000B pc=3FA78E30 cyc=44629477
|
||||
1 R reg=1 val=0005 pc=3FA79E50 cyc=44629558
|
||||
1 W reg=3 val=0055 pc=3FA79F00 cyc=44629580
|
||||
1 R reg=1 val=0001 pc=3FA79FB0 cyc=44629602
|
||||
1 W reg=E val=0000 pc=3FA7A060 cyc=44629624
|
||||
1 W reg=F val=0000 pc=3FA7A110 cyc=44629646
|
||||
1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44629668
|
||||
1 R reg=D val=00F0 pc=3FA7A320 cyc=44629702
|
||||
1 R reg=5 val=000B pc=3FA78E30 cyc=44647705
|
||||
1 R reg=1 val=0005 pc=3FA79E50 cyc=44647786
|
||||
1 W reg=3 val=0000 pc=3FA79F00 cyc=44647808
|
||||
1 R reg=1 val=0001 pc=3FA79FB0 cyc=44647830
|
||||
1 W reg=E val=0000 pc=3FA7A060 cyc=44647852
|
||||
1 W reg=F val=0000 pc=3FA7A110 cyc=44647874
|
||||
1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44647896
|
||||
1 R reg=D val=00F0 pc=3FA7A320 cyc=44647930
|
||||
1 R reg=5 val=000B pc=3FA78E30 cyc=44665934
|
||||
1 R reg=1 val=0007 pc=3FA7A3C0 cyc=44666004
|
||||
1 W reg=2 val=0008 pc=3FA7A3F0 cyc=44666010
|
||||
1 R reg=1 val=0003 pc=3FA7A440 cyc=44666018
|
||||
1 W reg=2 val=000A pc=3FA76010 cyc=44715338
|
||||
1 R reg=1 val=0012 pc=3FA761B0 cyc=44715379
|
||||
1 R reg=3 val=000A pc=3FA76360 cyc=44715419
|
||||
1 R reg=1 val=0012 pc=3FA761B0 cyc=44715444
|
||||
1 R reg=3 val=001F pc=3FA76360 cyc=44715484
|
||||
1 R reg=1 val=0010 pc=3FA761B0 cyc=44715509
|
||||
1 R reg=3 val=000A pc=3FA76360 cyc=44715549
|
||||
1 W reg=5 val=0000 pc=3FA78D10 cyc=44715718
|
||||
1 W reg=5 val=0007 pc=3FA78B40 cyc=44715843
|
||||
1 W reg=5 val=0000 pc=3FA78D10 cyc=44716071
|
||||
1 W reg=2 val=00FA pc=3FA778D0 cyc=44716176
|
||||
1 W reg=2 val=00CA pc=3FA77990 cyc=44716502
|
||||
1 W reg=2 val=002A pc=3FA77A30 cyc=44716823
|
||||
1 W reg=2 val=003A pc=3FA77AD0 cyc=44717144
|
||||
1 W reg=2 val=004A pc=3FA77B70 cyc=44717465
|
||||
1 W reg=2 val=005A pc=3FA77C10 cyc=44717786
|
||||
1 W reg=2 val=001A pc=3FA77CA0 cyc=44718106
|
||||
1 W reg=A val=00CA pc=3FA77990 cyc=44718497
|
||||
1 W reg=A val=002A pc=3FA77A30 cyc=44718818
|
||||
1 W reg=A val=003A pc=3FA77AD0 cyc=44719139
|
||||
1 W reg=A val=004A pc=3FA77B70 cyc=44719460
|
||||
1 W reg=A val=005A pc=3FA77C10 cyc=44719781
|
||||
1 W reg=A val=001A pc=3FA77CA0 cyc=44720101
|
||||
1 W reg=F val=0080 pc=3FA850F0 cyc=44720336
|
||||
1 R reg=D val=00F0 pc=3F2045A0 cyc=44720804
|
||||
1 W reg=D val=0000 pc=3F208830 cyc=44995716
|
||||
1 W reg=F val=00FF pc=3F208880 cyc=44995721
|
||||
@@ -0,0 +1,43 @@
|
||||
# DUART1 IRQ assert: ISR/SRA at the moment of the interrupt
|
||||
irq=1 isr=09 sra=0C cyc=43805849
|
||||
irq=1 isr=09 sra=04 cyc=43809940
|
||||
irq=1 isr=09 sra=04 cyc=43828170
|
||||
irq=1 isr=0A sra=01 cyc=43829472
|
||||
irq=1 isr=09 sra=04 cyc=43851607
|
||||
irq=1 isr=0A sra=01 cyc=43852909
|
||||
irq=1 isr=09 sra=04 cyc=43875044
|
||||
irq=1 isr=0A sra=01 cyc=43876346
|
||||
irq=1 isr=09 sra=04 cyc=43898481
|
||||
irq=1 isr=0A sra=01 cyc=43899784
|
||||
irq=1 isr=0A sra=09 cyc=43923222
|
||||
irq=1 isr=0C sra=00 cyc=43933971
|
||||
irq=1 isr=09 sra=0C cyc=44061742
|
||||
irq=1 isr=09 sra=04 cyc=44067135
|
||||
irq=1 isr=09 sra=04 cyc=44087969
|
||||
irq=1 isr=0A sra=01 cyc=44089271
|
||||
irq=1 isr=09 sra=04 cyc=44114011
|
||||
irq=1 isr=0A sra=01 cyc=44115313
|
||||
irq=1 isr=09 sra=04 cyc=44140052
|
||||
irq=1 isr=0A sra=01 cyc=44141354
|
||||
irq=1 isr=09 sra=04 cyc=44166093
|
||||
irq=1 isr=0A sra=01 cyc=44167395
|
||||
irq=1 isr=0A sra=09 cyc=44193438
|
||||
irq=1 isr=0C sra=00 cyc=44200001
|
||||
irq=1 isr=09 sra=0C cyc=44327797
|
||||
irq=1 isr=09 sra=04 cyc=44333190
|
||||
irq=1 isr=09 sra=04 cyc=44354024
|
||||
irq=1 isr=0A sra=21 cyc=44355326
|
||||
irq=1 isr=09 sra=04 cyc=44380066
|
||||
irq=1 isr=0A sra=21 cyc=44381368
|
||||
irq=1 isr=09 sra=04 cyc=44406107
|
||||
irq=1 isr=0A sra=21 cyc=44407409
|
||||
irq=1 isr=09 sra=04 cyc=44432148
|
||||
irq=1 isr=0A sra=01 cyc=44433450
|
||||
irq=1 isr=0A sra=09 cyc=44459493
|
||||
irq=1 isr=0C sra=00 cyc=44466068
|
||||
irq=1 isr=09 sra=0C cyc=44592754
|
||||
irq=1 isr=09 sra=04 cyc=44598148
|
||||
irq=1 isr=09 sra=04 cyc=44611168
|
||||
irq=1 isr=0B sra=05 cyc=44629398
|
||||
irq=1 isr=0B sra=05 cyc=44647626
|
||||
irq=1 isr=0B sra=07 cyc=44665855
|
||||
@@ -1506,7 +1506,16 @@ void duart_channel::tra_callback()
|
||||
rx_w(transmit_register_get_data_bit());
|
||||
}
|
||||
|
||||
// TxRDY is not set until the end of start bit time
|
||||
// TxRDY is not set until the end of start bit time.
|
||||
//
|
||||
// VT1200 NOTE: verified faithful to the fitted part (Signetics SCN2681
|
||||
// product specification, p.22 "Transmitter Disable Note": "TxRDY sets at
|
||||
// the end of the 'start bit' time. It is during the start bit that the
|
||||
// data in the transmit holding register is transferred to the transmit
|
||||
// shift register."). An earlier local VT1200 edit asserted TxRDY at
|
||||
// tra_complete() instead; that edit was REFUTED by this sentence (the
|
||||
// citation it used, p.7, describes the THR->TSR transfer but says nothing
|
||||
// about when TxRDY is set) and has been reverted. Do not re-apply it.
|
||||
if (++m_bits_transmitted > 1 && !m_tx_data_in_buffer && m_tx_enabled)
|
||||
{
|
||||
SR |= STATUS_TRANSMITTER_READY;
|
||||
|
||||
Reference in new issue
Block a user