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docs: next level-1 gate is HOST PORT (window 0x6400000); evidence and approach recorded
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@@ -987,3 +987,37 @@ condition it fails on, model it, re-run the console capture.
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1. Model the host DUART (DUART1 channel A) enough for the level-1 HOST PORT test
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(bit 0x3F...); the DUARTs are unmodelled and are the current gate.
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2. Keep using cap.lua to read which test fails next -- the loop is now repeatable.
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## Next gate: level-1 HOST PORT (DUART1 channel A) — evidence so far
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With video memory mapped and REFCNT advancing, the level-1 sequence advanced to:
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```
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'LEVEL1/2 ERROR -> HOST PORT - 15 ' (error-string file 0x17938D, handler 0x07FBD3C2)
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```
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This is DUART1 channel A per the service guide's level-1 list — a local-loopback test on the
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host serial port. The DUARTs are **not modelled**, so it fails.
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**Evidence** (`VT1200_BOARD_LOG`, 700 frames, with the video-memory fixes in place) — the
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most-touched unmodelled register during that window:
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```
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31 W 06400002 <- by far the hottest; a DUART register being written repeatedly
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13 W 0620000A 13 W 06200002
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12 W 0640000A 6 R 0640000D 6 R 06200001
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```
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So window **`0x6400000`** (the driver's address units; offset `0x02`) is where the host-port
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test lives. A loopback test writes the transmit register and reads the receive register, so
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the next step is to find which offsets it reads back and give the window DUART-like
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behaviour.
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**Preferred approach:** wire MAME's `SCN2681`/`MC68681` device at that window (it is the
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right part, and MAME has it), rather than hand-rolling a loopback. Fallback: a stateful
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transparent register file in the driver with write-to-TX appearing at RX.
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**Context for scheduling:** level 1 is 15 tests. One now passes (video memory). The method is
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settled and repeatable — identify the test from the console, find the condition, model it,
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re-run — but each remaining gate (DUARTs, keyboard, mouse, NVRAM, LANCE, video RAM) needs a
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modelled device. Level 0 already passes.
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