docs: next level-1 gate is HOST PORT (window 0x6400000); evidence and approach recorded

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SDD committed 2026-10-16 11:01:39 +03:00
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@@ -987,3 +987,37 @@ condition it fails on, model it, re-run the console capture.
1. Model the host DUART (DUART1 channel A) enough for the level-1 HOST PORT test
(bit 0x3F...); the DUARTs are unmodelled and are the current gate.
2. Keep using cap.lua to read which test fails next -- the loop is now repeatable.
## Next gate: level-1 HOST PORT (DUART1 channel A) — evidence so far
With video memory mapped and REFCNT advancing, the level-1 sequence advanced to:
```
'LEVEL1/2 ERROR -> HOST PORT - 15 ' (error-string file 0x17938D, handler 0x07FBD3C2)
```
This is DUART1 channel A per the service guide's level-1 list — a local-loopback test on the
host serial port. The DUARTs are **not modelled**, so it fails.
**Evidence** (`VT1200_BOARD_LOG`, 700 frames, with the video-memory fixes in place) — the
most-touched unmodelled register during that window:
```
31 W 06400002 <- by far the hottest; a DUART register being written repeatedly
13 W 0620000A 13 W 06200002
12 W 0640000A 6 R 0640000D 6 R 06200001
```
So window **`0x6400000`** (the driver's address units; offset `0x02`) is where the host-port
test lives. A loopback test writes the transmit register and reads the receive register, so
the next step is to find which offsets it reads back and give the window DUART-like
behaviour.
**Preferred approach:** wire MAME's `SCN2681`/`MC68681` device at that window (it is the
right part, and MAME has it), rather than hand-rolling a loopback. Fallback: a stateful
transparent register file in the driver with write-to-TX appearing at RX.
**Context for scheduling:** level 1 is 15 tests. One now passes (video memory). The method is
settled and repeatable — identify the test from the console, find the condition, model it,
re-run — but each remaining gate (DUARTs, keyboard, mouse, NVRAM, LANCE, video RAM) needs a
modelled device. Level 0 already passes.