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reference: DUART counter/timer period when CTUR/CTLR unprogrammed -- datasheet does not settle it
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# MAME `mc68681` counter/timer period when `CTUR`/`CTLR` are never programmed
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Task: the VT1200 stub level-1 run wedges in a DUART1 counter-ready interrupt storm
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because `ACR = 0x60` selects timer mode while `CTUR`/`CTLR` are never written.
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MAME substitutes `std::max(CTR.w.l, 1)` and re-arms every tick. Determine from the
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datasheet what the fitted part (Signetics/Philips **SCN2681**) actually does when the
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counter is unprogrammed.
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**Verdict: the datasheet does NOT settle it.** Details below; the reasoning is as
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important as the quotes, and the conclusion is "stop, do not guess."
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Sources (all local, in `reference/duart-datasheet/`): primary **SCN2681** Philips
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1995-05-01 product specification (`SCN2681-transputer.pdf`/`.txt`) — the part fitted;
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corroboration **SCC2681** Philips 2004-04-06 (`SCC2681-nxp`), **SCN68681** Signetics
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1998-09-04 (`SCN68681-xdevs`), **MC68HC681** Motorola User's Manual
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(`MC68681UM-nxp`). Page numbers are the printed page numbers (each page footer reads
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`1995 May 1 <n>` for the SCN2681, etc.).
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---
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## 1. What the datasheet says
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### 1a. There is no "0 means 65536" convention — the counter counts *through* 0
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SCN2681, printed page 16 (also SCN68681 p. 17, SCC2681 p. 19):
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> "In the counter mode, the C/T counts down the number of pulses loaded into CTUR and
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> CTLR by the CPU. Counting begins upon receipt of a counter command. Upon reaching
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> terminal count (000016), the counter ready interrupt bit (ISR[3]) is set. The counter
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> continues counting past the terminal count until stopped by the CPU."
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SCN68681, printed page 9, "Operation Control":
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> "The counter operates as a down counter and sets its output bit in the ISR (Interrupt
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> Status Register) **each time it passes through 0**."
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Motorola MC68HC681 User's Manual, §3.5.1 (printed page 3-6):
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> "The value (preload value) stored in the concatenation of the C/T upper register
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> (CTUR) and the C/T lower register (CTLR) **can be from 000116 through FFFF16** …
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> When the counter counts from 000116 to 000016 (terminal count), the C/T-ready bit in
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> the interrupt status register (ISR[3]) is set. … **After 000016 the counter counts to
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> FFFF16, and continues counting down from there.**"
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So 0000 is the **terminal count**, not 65536; the counter saturates/reloads downward, it
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does not wrap modulo 65536. **The "0 = 65536" hypothesis is refuted.**
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### 1b. Zero is *below the minimum legal preload* — MAME's clamp to 1 is not derivable
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SCN2681, printed page 16, "CTUR and CTLR – Counter/Timer Registers":
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> "The CTUR and CTLR hold the eight MSBs and eight LSBs, respectively, of the value to
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> be used by the counter/timer in either the counter or timer modes of operation.
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> **The minimum value which may be loaded into the CTUR/CTLR registers is 000216.** Note
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> that these registers are write-only and cannot be read by the CPU."
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Motorola gives the same idea with a different floor: "can be from **000116** through
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FFFF16" (MC68HC681 UM §3.5, p. 3-6). In timer mode the SCN2681 says the square-wave
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period is "twice the value (in clock periods) of the CTUR and CTLR" — so a preload of 2
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is the fastest legal half-period; a preload of 0 is not a legal state at all.
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Consequence: MAME's `max(CTR.w.l, 1)` yields a half-period of **1** clock tick, which
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**no legal preload can produce** (Philips floor = 2, Motorola floor = 1 but never 0).
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It is a modelling choice, not a datasheet value.
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### 1c. But the datasheet never says what an *unprogrammed* counter does
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The datasheet defines the **legal** range and says nothing about 0. It also never
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defines the **power-up/reset** value of CTUR/CTLR — and the reset description is
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internally contradictory:
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SCN2681, printed page 2, `RESET` pin description:
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> "Reset: A High level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts
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> OP0–OP7 in the High state, **stops the counter/timer**, and puts Channels A and B in
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> the inactive state, with the TxDA and TxDB outputs in the mark (High) state."
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Note that `CTUR`/`CTLR` are **not** in the list of registers reset clears.
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SCN2681, printed page 16, "Counter/Timer" (the *same* datasheet):
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> "**On power up and after reset, the timer/counter runs in timer mode and can only be
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> restarted. Because it cannot be shut off or stopped, and runs continuously in timer
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> mode**, it is recommended that at initialization, the output port (OP3) should be
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> masked off through the OPCR[3:2] = 00 until the T/C is programmed to the desired
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> operational state."
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and, on the same page:
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> "If new values have not been loaded, the previous count values are preserved and used
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> for the next count cycle."
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So on the fitted part: after reset the C/T **is running** in timer mode (the counter
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section), yet the reset pin description says reset **stops** it. The datasheet does not
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state the reset preload value, and the counter section's "runs continuously" statement
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means the counter is armed with *whatever* value CTUR/CTLR holds — which at power-up is
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not defined.
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### 1d. The family differs on this exact point (as asked)
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SCC2681 (2004), printed page 19:
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> "On power up and after reset the timer/counter **comes up stopped** and in the timer
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> mode. It will require a start counter command (a read at address 0xE) to start it.
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> Because it cannot be shut off or stopped once started, and runs continuously in timer
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> mode, it is recommended that at initialization, the output port (OP3) should be masked
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> off through the OPCR[3:2] = 00 until the T/C is programmed to the desired operational
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> state."
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Motorola MC68HC681 UM, §3.5 (p. 3-6/3-7) is silent on "stopped at reset":
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> "At power-up and after reset, the C/T operates in timer mode."
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> "In timer mode, the C/T runs continuously; the CPU cannot start or stop it."
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So the **fitted SCN2681 says the counter runs after reset**; the later **SCC2681 says it
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comes up stopped** and needs a Start Counter command. This is a genuine family split
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and, by itself, prevents any single unambiguous answer for "unprogrammed".
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---
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## 2. MAME's exact behaviour
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File: `/home/arti/code/k-space/mame0289/src/devices/machine/mc68681.cpp`.
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Reset (`duart_base_device::device_reset`, lines 275–289) zeroes the preload and quotes
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the SCN2681 reset line:
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```c++
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275: void duart_base_device::device_reset()
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276: {
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277: ACR = 0; /* Interrupt Vector Register */
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...
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282: CTR.d = 0; /* Counter/Timer Preset Value */
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283: // "reset clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR) puts OP0-7 in the high state, stops the counter/timer, and puts channels a/b in the inactive state"
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```
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The timer callback reloads the preload every half period with the clamp:
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```c++
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500: TIMER_CALLBACK_MEMBER(duart_base_device::duart_timer_callback)
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501: {
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502: if (ACR & 0x40)
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503: {
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504: // Timer mode
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505: half_period ^= 1;
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...
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536: if (!half_period)
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537: set_ISR_bits(INT_COUNTER_READY);
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538:
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539: int count = std::max(CTR.w.l, uint16_t(1)); // <-- clamp
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540: start_ct(count);
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541: }
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542: else
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543: {
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...
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548: // Counter mode
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549: set_ISR_bits(INT_COUNTER_READY);
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550: start_ct(0xffff);
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551: }
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552: }
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```
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The same clamp is reached on the two other arming paths — the **Start-Counter command**
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(register `0x0e` read) and the **ACR write that enters timer mode**:
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```c++
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735: case 0x0e: /* Start counter command */
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736: {
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737: if (ACR & 0x40)
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738: {
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739: // Reset the timer
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740: half_period = 0;
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741: }
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742:
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743: int count = std::max(CTR.w.l, uint16_t(1)); // <-- clamp
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744: start_ct(count);
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745: break;
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746: }
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```
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```c++
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960: case 0x04: /* ACR */
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961: {
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962: uint8_t old_acr = ACR;
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963: ACR = data;
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...
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967: if ((old_acr ^ data) & 0x40)
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968: {
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969: if (data & 0x40)
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970: {
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971: // Entering timer mode
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972: uint16_t count = std::max(CTR.w.l, uint16_t(1)); // <-- clamp
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973: half_period = 0;
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974:
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975: start_ct(count);
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976: }
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```
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and the arming primitive itself (lines 494–498):
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```c++
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494: void duart_base_device::start_ct(int count)
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495: {
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496: uint32_t clock = get_ct_rate();
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497: duart_timer->adjust(attotime::from_ticks(count, clock), 0);
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498: }
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```
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Reading `CTUR`/`CTLR` (lines 999–1005) only updates `CTR`, so with no write `CTR.w.l`
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stays 0, every arm uses count = 1, and the timer callback sets `ISR[3]` every second
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callback — hence the ~229-CPU-cycle storm reported in
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`harness/mame/LEVEL1_CONTINUE_REPORT.md`.
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**Measured for the VT1200 run:** DUART1 register 4 (ACR) is written once, `0x60`, at PC
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`3FA71CB0`; registers 6/7 (CTUR/CTLR) are **never written**. Confirmed from the harness
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logs (`hp_board.log`/`board-hp.log` line 96: `W 06400004 pc=3FA71CB0 val=0060`; no
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`06400006`/`06400007` write anywhere in the run). The clamp is therefore exactly the
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line in play.
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---
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## 3. Verdict
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**The datasheet does not settle it.**
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What *is* settled:
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* `0` does **not** mean 65536 — the C/T is a down-counter that passes through terminal
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count `0000` and keeps counting down (SCN2681 p. 16; SCN68681 p. 9).
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* `0` is **below the minimum legal preload** (SCN2681/SCC2681/SCN68681: `0002`;
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MC68HC681: `0001`). MAME's clamp to `1` yields a period **no legal preload can
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produce**, so it is a model invention, not a datasheet value.
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What is **not** settled:
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* The datasheet defines no behaviour for preload `0` (it is simply out of range).
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* It does not define the power-up/reset value of `CTUR`/`CTLR` — reset does not clear
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them (SCN2681 p. 2), and the reset state of the counter is self-contradictory in the
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SCN2681 itself ("stops the counter/timer" p. 2 vs "runs in timer mode and can only be
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restarted … cannot be shut off or stopped" p. 16).
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* The family disagrees: SCN2681 (fitted) runs after reset; SCC2681 comes up stopped and
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needs a Start Counter command.
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So we cannot derive a trustworthy "correct" period from the datasheet. We can say only
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that MAME's specific value is not datasheet-derived; every alternative (2, 1, "stopped
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until Start") is likewise not settled by the fitted part's own contradicting text.
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**No change is justified on datasheet grounds. Do not apply anything.** (The task called
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this outcome in advance: a "does not settle it" result means stop rather than guess.)
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Note on scope: the harness report `LEVEL1_CONTINUE_REPORT.md` §"The wall, named" already
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described this as upstream `max(CTR,1)` behaviour and did not change MAME, which was
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correct under this finding.
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---
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## 4. Minimal change — stated but **NOT applied**
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Because the verdict is "does not settle it", there is **no datasheet-backed edit** to
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propose, and none is made. For the record of what a *non*-datasheet-backed "make it
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slower" patch would look like (so the owner can see the shape and reject it), the
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candidate would be at three sites in `src/devices/machine/mc68681.cpp`:
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```c++
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// lines 539, 743, 972 — candidate only, NOT applied:
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-int count = std::max(CTR.w.l, uint16_t(1));
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+int count = std::max(CTR.w.l, uint16_t(2)); // or 0xffff, etc.
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```
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**Revert note for that candidate:** each of the three edits is a single-token change on
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lines 539, 743, and 972; reverting is restoring `uint16_t(1)` on each. **Do not apply
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this** — it is arbitrary: 2 matches the Philips floor but not the Motorola part, it still
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invents behaviour for an illegal preload, and the datasheet gives no basis for choosing
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it over "the counter stays stopped" (SCC2681) or "runs with an undefined preload"
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(SCN2681). Choosing any value here would be exactly the "model quietly invents
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behaviour" failure this check exists to catch.
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---
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## 5. Does the skip path hit the same fallback?
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**Yes, the fallback is exercised — but it is harmless there, so this is not worth much
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as a separate bug.**
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* The skip path (`VT1200_SKIP_LEVEL1=1`) never runs the level-1 counter test, so the
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`IMR = 0x08` (counter-ready only) write that creates the storm never happens.
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* The OS *does* leave `CTUR`/`CTLR` unprogrammed on the DUARTs it configures: the OS
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bring-up log shows `W 06200004=0060 ACR` and no write to `06200006`/`06200007`
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(`harness/mame/OS_BRINGUP_REPORT.md` §8.3). And during the OS, the DUART1 ISR reads
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back `0x0009` (`R 06400005 pc=3FB43900 val=0009`, §2) — bit 3 set, i.e. **the counter
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fallback is running and setting `ISR[3]` on DUART1 as well**.
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* It still does not storm because the OS never enables (or services) the counter-ready
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interrupt: it programs `IMR = 0x33` on DUART2 (no bit 3; `OS_BRINGUP_REPORT.md` §4.1)
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and its dispatcher masks the ISR with `0x66` (bits 1,2,5,6 — not bit 3). MAME's
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`update_interrupts()` raises the IRQ only for masked bits, so `ISR[3]` being set is
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invisible.
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So: the skip path hits the *same model fallback* (unprogrammed preload in timer mode),
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but only the **aborted level-1 test** turns it into a storm by enabling solely the
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counter-ready interrupt (`IMR = 0x08`) on a dispatcher that handles bit 3. The storm is
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a level-1-path symptom; the skip/OS path is unaffected. That lowers the value of chasing
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this fallback — it is not what blocks the OS.
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---
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## Reproduction / provenance
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* ROM `harness/mame/roms/vt1200/vt1200_v22.bin`, md5 `b46a3e442ccb86134d2356bd70d22fd2`
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(unchanged; nothing in the MAME tree or `harness/mame/` was modified by this task).
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* MAME source read-only: `/home/arti/code/k-space/mame0289/src/devices/machine/mc68681.cpp`
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lines 275–289, 494–498, 500–553, 735–746, 960–976, 999–1005.
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* Datasheet quotes from `reference/duart-datasheet/SCN2681-transputer.txt` (printed
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pages 2 and 16), `SCN68681-xdevs.txt` (page 9), `SCC2681-nxp.txt` (page 19),
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`MC68681UM-nxp.txt` (§3.5, pages 3-6/3-7).
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