docs: last authorised timing change tested (idle-path transmit start) -- real deviation, not the cause; reverted

Mechanism quantified first, per byte over the 5-byte burst: start latency 2605, 15442,
20652, 20650, 20652 cycles -- i.e. 1 bit for the idle byte 0 only, then constant because
later characters are pinned by the previous character's end.  It does NOT accumulate.

Implemented the authorised contained change (write_TX idle path begins the start bit
immediately; new start_now parameter in emu/diserial.{h,cpp}; buffered path and receive
side untouched; SCN2681 16x-clock citations recorded).  Result: byte 0's latency 2605 -> 5
cycles, nothing else moved, and the outcome was identical -- same three failing checks,
same returns (L3FA71BC0=0x00900040, L3FA753D0=3, L3FA6E4B0=6), same console line.

DECISION: reverted.  The deviation is real but the change does not move the symptom and is
only a partial fidelity fix (a faithful model would clock the transmitter at 16x).  Keeping
a change that buys nothing adds noise.  MAME tree is back to edit 2 (overrun latch) only
plus the edit-1 refutation note; emu/diserial.{h,cpp} unmodified.

DUART_REPORT.md now carries the full handover: established / ruled out / remaining
discrepancy / open deviations.  Acceptance still fails; regression holds.

harness/mame/DUART_REPORT.md

@@ -965,3 +965,95 @@ Two corrections:
    carries adjacent frame data as well as flags — so "return == 0" is stricter than "all
    checks pass" unless that word is zero.  Worth confirming before treating `L3FA71BC0`'s
    return as a pure flag word.
+
+---
+
+# LAST AUTHORISED TIMING CHANGE — tested, did not move the symptom, reverted
+
+## Mechanism quantified first (as required)
+
+Per-byte, same 5-byte burst, current tree (`hp_lat.log` / `hp_lat.out`).  Character start
+= first transmitted bit (`VTCHSTART`); THRA write = `VT1200_DUARTLOG`:
+
+| byte | THRA write | char start | start latency |
+|---|---|---|---|
+| 0 | 44592939 | 44595544 | **2605** |
+| 1 | 44598330 | 44613772 | **15442** |
+| 2 | 44611350 | 44632002 | **20652** |
+| 3 | 44629580 | 44650230 | **20650** |
+| 4 | 44647808 | 44668460 | **20652** |
+
+So the transmit-start latency does **not accumulate**: it is 1 bit for the *idle* byte 0
+only, then constant (~1.13 char) because every later character is pinned by the *previous*
+character's end (the buffered path).  The owner's magnitude argument therefore predicted
+the deviation could not be the cause, and this measurement confirms it.
+
+## The change, tested
+
+Implemented as authorised, contained to the idle path: `write_TX`'s idle branch calls
+`transmit_register_setup(data, true)`, which schedules the first bit immediately instead of
+at the next 1x tick (new `start_now` parameter in `emu/diserial.{h,cpp}`); the buffered
+path and the whole receive side untouched.  Citations recorded in the edit: SCN2681
+"The clock outputs from the BRG are at 16X the actual baud rate", the 1x/16x external clock
+note, `CSRA` = receiver/transmitter clock select, and the receiver's "each 16X clock for
+7-1/2 clocks" sampling note.
+
+Result (`hp_lat2.log`, `hp_lat2.out`): byte 0's start latency went 2605 -> **5** cycles, and
+**nothing else changed** — bytes 1-4 stayed 15442/20652/20650/20652, the receive completions
+moved with the writes, and the outcome was **identical**:
+
+```
+flag-set sites that fire:  BC0/c6 x3, BC0/cE (summary) x1, RX/c0 x1, RX/c1 x1   (unchanged)
+returns:                   L3FA71BC0 = 0x00900040, L3FA753D0 = 3, L3FA767E0 = 0, L3FA6E4B0 = 6
+console:                   'LEVEL1/2 ERROR -> HOST PORT - 15'                    (unchanged)
+```
+
+## Decision: REVERTED (not kept)
+
+The deviation is real and datasheet-backed, but the change does **not** move the symptom,
+and it is only a *partial* fidelity fix — a fully faithful model would clock the transmitter
+at 16x (the real part), which is a much larger change, and the buffered path would still
+quantise to a bit.  Keeping a partial change that buys nothing adds noise to the tree, so it
+is reverted; the deviation and its citations are recorded here instead.  The MAME tree is
+back to: **edit 2 (overrun latch) only**, plus the inline refutation note for edit 1.
+`emu/diserial.{h,cpp}` are **unmodified**.
+
+# HANDOVER — full picture
+
+**Established.**
+* Root cause of the original missing transmit: the DUART IRQ was unwired; wiring
+  DUART1 -> INT1 makes THRA get written (0 -> 20/run) and fixes the direct SRA/RHRA checks.
+* The quantity to zero is `L3FA6E4B0`'s return, verified at the call site and at the
+  handler (`0x400` -> HOST PORT).
+* Exactly **three** checks still fail, all reading the DUART ISR's own SRA snapshots
+  (writers confirmed by proxy: ISR TxRDYA path `3FA79E30`/`3FA7A3A0` for `+0x3c0`/`+0x3d0`,
+  ISR RxRDYA path `3FA79690` for `struct[i].0x60`):
+  - `L3FA71BC0` `c6` (`3FA73970`): the ISR's received status has SRA bit 5 = **PARITY
+    ERROR** in 3 combinations (`0x0021`), clean (`0x0001`) otherwise.
+  - `L3FA753D0` `c1`/`c0` (`3FA760E0`/`3FA76050`): the index4/index5 snapshots lack
+    **FFULL**/**OVR** — a receive-count lag at the snapshot boundary.
+* The direct loopback **data** path is correct (RHRA compares pass; received bytes
+  `0x0A,0x1F,0x0A` as expected).
+
+**Ruled out.** external responder; FIFO depth (faithful); loopback-clock deviation as a
+cause; the counter/COUNTER_READY lead; INT1-vs-INT2 and the OP interrupt outputs; frame
+width; CSRA rate mismatch; and now the transmit-start latency (real, but non-accumulating
+and provably not the cause).
+
+**Remaining discrepancy.** The ISR's SRA snapshots differ from the firmware's expectation
+in two ways: a ~1-byte receive-count lag, and a parity error in 3 parity-enabled
+combinations.  Both are sub-bit phase/sampling artifacts, not data-path failures.
+
+**Open MAME deviations.** (1) transmit-start 16x quantisation — real, tested, not the cause;
+(2) loopback receive clock (SCN2681 p.12 item 2) — real, phase-only, not the cause;
+(3) `write_CR` bit1 clears `RxRDY` where the datasheet preserves FIFO status — minor;
+(4) `COUNTER_READY` set at the Start-Counter read — not biting; (5) pre-existing `tms34010`
+REFCNT local edit.
+
+**Acceptance:** `LEVEL1/2 ERROR -> HOST PORT - 15` — still present; no next gate.
+**Regression:** holds (`PC=3FDCE400 samples=199`).
+
+**Suggested next step (not this gate).** The renderer is independent of this gate; the
+remaining host-port discrepancy is a sub-bit phase artifact in the DUART ISR's SRA
+snapshots and would need either a 16x-clock transmit model or a receive-phase rework to
+chase further.

harness/mame/hp_lat.log

@@ -0,0 +1,443 @@
+# win kind reg val pc -- every DUART access (not de-duplicated)
+1 W reg=D val=0000 pc=3F2000B0 cyc=7
+1 R reg=F val=00FF pc=3F200100 cyc=12
+1 W reg=F val=00FF pc=3F200100 cyc=12
+1 R reg=E val=00FF pc=3F200150 cyc=15
+1 W reg=E val=000F pc=3F200150 cyc=15
+1 R reg=F val=00FF pc=3F200250 cyc=29
+1 W reg=F val=0001 pc=3F200250 cyc=29
+1 R reg=D val=00F0 pc=3F200380 cyc=46
+1 R reg=D val=00F0 pc=3F200A20 cyc=2123
+1 R reg=D val=00F0 pc=3F202650 cyc=2715
+1 R reg=D val=00F0 pc=3F2045A0 cyc=465049
+1 R reg=E val=00FF pc=3F2042D0 cyc=576004
+1 W reg=E val=0001 pc=3F2042D0 cyc=576004
+1 R reg=D val=00F0 pc=3F204300 cyc=576005
+1 W reg=D val=0000 pc=3FDF1150 cyc=576167
+1 W reg=F val=0001 pc=3FDF1190 cyc=576171
+1 R reg=D val=00F0 pc=3FDF7DE0 cyc=1297177
+1 R reg=D val=00F0 pc=3F2045A0 cyc=1897379
+1 W reg=2 val=00CA pc=3FA90A00 cyc=3737622
+1 W reg=2 val=002A pc=3FA90AB0 cyc=3737945
+1 W reg=2 val=003A pc=3FA90B60 cyc=3738268
+1 W reg=2 val=004A pc=3FA90C10 cyc=3738591
+1 W reg=2 val=005A pc=3FA90CC0 cyc=3738914
+1 W reg=2 val=001A pc=3FA90D60 cyc=3739236
+1 W reg=A val=00CA pc=3FA90E10 cyc=3739559
+1 W reg=A val=002A pc=3FA90EC0 cyc=3739882
+1 W reg=A val=003A pc=3FA90F70 cyc=3740205
+1 W reg=A val=004A pc=3FA91020 cyc=3740528
+1 W reg=A val=005A pc=3FA910D0 cyc=3740851
+1 W reg=A val=001A pc=3FA91170 cyc=3741173
+1 W reg=F val=0080 pc=3FA7C330 cyc=3744820
+1 R reg=D val=00F0 pc=3F2045A0 cyc=10040220
+1 R reg=D val=00F0 pc=3F2045A0 cyc=15792800
+1 R reg=D val=00F0 pc=3F2045A0 cyc=15926711
+1 R reg=D val=00F0 pc=3F2045A0 cyc=34826663
+1 W reg=2 val=00FA pc=3FA778D0 cyc=43724635
+1 W reg=2 val=00CA pc=3FA77990 cyc=43724961
+1 W reg=2 val=002A pc=3FA77A30 cyc=43725282
+1 W reg=2 val=003A pc=3FA77AD0 cyc=43725603
+1 W reg=2 val=004A pc=3FA77B70 cyc=43725924
+1 W reg=2 val=005A pc=3FA77C10 cyc=43726245
+1 W reg=2 val=001A pc=3FA77CA0 cyc=43726565
+1 W reg=A val=00CA pc=3FA77990 cyc=43726956
+1 W reg=A val=002A pc=3FA77A30 cyc=43727277
+1 W reg=A val=003A pc=3FA77AD0 cyc=43727598
+1 W reg=A val=004A pc=3FA77B70 cyc=43727919
+1 W reg=A val=005A pc=3FA77C10 cyc=43728240
+1 W reg=A val=001A pc=3FA77CA0 cyc=43728560
+1 W reg=2 val=00FA pc=3FA778D0 cyc=43735282
+1 W reg=2 val=00CA pc=3FA77990 cyc=43735608
+1 W reg=2 val=002A pc=3FA77A30 cyc=43735929
+1 W reg=2 val=003A pc=3FA77AD0 cyc=43736250
+1 W reg=2 val=004A pc=3FA77B70 cyc=43736571
+1 W reg=2 val=005A pc=3FA77C10 cyc=43736892
+1 W reg=2 val=001A pc=3FA77CA0 cyc=43737212
+1 W reg=A val=00CA pc=3FA77990 cyc=43737603
+1 W reg=A val=002A pc=3FA77A30 cyc=43737924
+1 W reg=A val=003A pc=3FA77AD0 cyc=43738245
+1 W reg=A val=004A pc=3FA77B70 cyc=43738566
+1 W reg=A val=005A pc=3FA77C10 cyc=43738887
+1 W reg=A val=001A pc=3FA77CA0 cyc=43739207
+1 W reg=5 val=0007 pc=3FA78B40 cyc=43739320
+1 W reg=D val=0000 pc=3FA704E0 cyc=43739379
+1 W reg=4 val=0060 pc=3FA71CB0 cyc=43739476
+1 W reg=2 val=003A pc=3FA71F20 cyc=43739539
+1 W reg=2 val=002A pc=3FA71FD0 cyc=43739862
+1 W reg=2 val=004A pc=3FA72080 cyc=43740185
+1 W reg=2 val=001A pc=3FA72120 cyc=43740507
+1 W reg=1 val=0088 pc=3FA72220 cyc=43740837
+1 W reg=0 val=0012 pc=3FA73090 cyc=43745391
+1 W reg=0 val=0080 pc=3FA731B0 cyc=43745728
+1 W reg=2 val=0005 pc=3FA73260 cyc=43805849
+1 R reg=5 val=0009 pc=3FA78E30 cyc=43805931
+1 R reg=1 val=000C pc=3FA79E50 cyc=43806012
+1 W reg=3 val=00AA pc=3FA79F00 cyc=43806034
+1 R reg=1 val=0000 pc=3FA79FB0 cyc=43806056
+1 W reg=E val=0000 pc=3FA7A060 cyc=43806078
+1 W reg=F val=0000 pc=3FA7A110 cyc=43806100
+1 R reg=D val=00F0 pc=3FA7A1C0 cyc=43806122
+1 R reg=D val=00F0 pc=3FA7A320 cyc=43806156
+1 R reg=5 val=0009 pc=3FA78E30 cyc=43810019
+1 R reg=1 val=0004 pc=3FA79E50 cyc=43810100
+1 W reg=3 val=00FF pc=3FA79F00 cyc=43810122
+1 R reg=1 val=0000 pc=3FA79FB0 cyc=43810144
+1 W reg=E val=0000 pc=3FA7A060 cyc=43810166
+1 W reg=F val=0000 pc=3FA7A110 cyc=43810188
+1 R reg=D val=00F0 pc=3FA7A1C0 cyc=43810210
+1 R reg=D val=00F0 pc=3FA7A320 cyc=43810244
+1 R reg=5 val=0009 pc=3FA78E30 cyc=43828249
+1 R reg=1 val=0004 pc=3FA79E50 cyc=43828330
+1 W reg=3 val=00AA pc=3FA79F00 cyc=43828352
+1 R reg=1 val=0000 pc=3FA79FB0 cyc=43828374
+1 W reg=E val=0000 pc=3FA7A060 cyc=43828396
+1 W reg=F val=0000 pc=3FA7A110 cyc=43828418
+1 R reg=D val=00F0 pc=3FA7A1C0 cyc=43828440
+1 R reg=D val=00F0 pc=3FA7A320 cyc=43828474
+1 R reg=5 val=000A pc=3FA78E30 cyc=43829551
+1 R reg=1 val=0001 pc=3FA796D0 cyc=43829633
+1 R reg=3 val=002A pc=3FA79780 cyc=43829655
+1 R reg=1 val=0000 pc=3FA79830 cyc=43829677
+1 R reg=D val=00F0 pc=3FA798E0 cyc=43829699
+1 R reg=D val=00F0 pc=3FA79A20 cyc=43829733
+1 R reg=5 val=0009 pc=3FA78E30 cyc=43851686
+1 R reg=1 val=0004 pc=3FA79E50 cyc=43851767
+1 W reg=3 val=0055 pc=3FA79F00 cyc=43851789
+1 R reg=1 val=0000 pc=3FA79FB0 cyc=43851811
+1 W reg=E val=0000 pc=3FA7A060 cyc=43851833
+1 W reg=F val=0000 pc=3FA7A110 cyc=43851855
+1 R reg=D val=00F0 pc=3FA7A1C0 cyc=43851877
+1 R reg=D val=00F0 pc=3FA7A320 cyc=43851911
+1 R reg=5 val=000A pc=3FA78E30 cyc=43852988
+1 R reg=1 val=0001 pc=3FA796D0 cyc=43853070
+1 R reg=3 val=007F pc=3FA79780 cyc=43853092
+1 R reg=1 val=0000 pc=3FA79830 cyc=43853114
+1 R reg=D val=00F0 pc=3FA798E0 cyc=43853136
+1 R reg=D val=00F0 pc=3FA79A20 cyc=43853170
+1 R reg=5 val=0009 pc=3FA78E30 cyc=43875123
+1 R reg=1 val=0004 pc=3FA79E50 cyc=43875204
+1 W reg=3 val=0000 pc=3FA79F00 cyc=43875226
+1 R reg=1 val=0000 pc=3FA79FB0 cyc=43875248
+1 W reg=E val=0000 pc=3FA7A060 cyc=43875270
+1 W reg=F val=0000 pc=3FA7A110 cyc=43875292
+1 R reg=D val=00F0 pc=3FA7A1C0 cyc=43875314
+1 R reg=D val=00F0 pc=3FA7A320 cyc=43875348
+1 R reg=5 val=000A pc=3FA78E30 cyc=43876425
+1 R reg=1 val=0001 pc=3FA796D0 cyc=43876507
+1 R reg=3 val=002A pc=3FA79780 cyc=43876529
+1 R reg=1 val=0000 pc=3FA79830 cyc=43876551
+1 R reg=D val=00F0 pc=3FA798E0 cyc=43876573
+1 R reg=D val=00F0 pc=3FA79A20 cyc=43876607
+1 R reg=5 val=0009 pc=3FA78E30 cyc=43898560
+1 R reg=1 val=0004 pc=3FA7A3C0 cyc=43898630
+1 W reg=2 val=0008 pc=3FA7A3F0 cyc=43898636
+1 R reg=1 val=0000 pc=3FA7A440 cyc=43898644
+1 R reg=5 val=000A pc=3FA78E30 cyc=43899863
+1 R reg=1 val=0001 pc=3FA796D0 cyc=43899945
+1 R reg=3 val=0055 pc=3FA79780 cyc=43899967
+1 R reg=1 val=0000 pc=3FA79830 cyc=43899989
+1 R reg=D val=00F0 pc=3FA798E0 cyc=43900011
+1 R reg=D val=00F0 pc=3FA79A20 cyc=43900045
+1 R reg=5 val=000A pc=3FA78E30 cyc=43923301
+1 R reg=1 val=0009 pc=3FA796D0 cyc=43923383
+1 R reg=3 val=0000 pc=3FA79780 cyc=43923405
+1 R reg=1 val=0008 pc=3FA79830 cyc=43923427
+1 R reg=D val=00F0 pc=3FA798E0 cyc=43923449
+1 R reg=D val=00F0 pc=3FA79A20 cyc=43923483
+1 W reg=2 val=000A pc=3FA73420 cyc=43931657
+1 W reg=2 val=002A pc=3FA74BE0 cyc=43933007
+1 W reg=2 val=002B pc=3FA74C80 cyc=43933329
+1 W reg=2 val=004A pc=3FA74D10 cyc=43933650
+1 W reg=2 val=0065 pc=3FA74DA0 cyc=43933971
+1 R reg=5 val=000F pc=3FA78E30 cyc=43934053
+1 R reg=1 val=008D pc=3FA78FD0 cyc=43934094
+1 W reg=2 val=0055 pc=3FA79010 cyc=43934101
+1 W reg=2 val=0075 pc=3FA790C0 cyc=43934424
+1 R reg=1 val=008D pc=3FA79AE0 cyc=43934494
+1 R reg=3 val=0000 pc=3FA79B00 cyc=43934499
+1 W reg=2 val=0002 pc=3FA79B60 cyc=43934508
+1 R reg=1 val=000C pc=3FA79BB0 cyc=43934516
+1 R reg=5 val=000D pc=3FA78E30 cyc=43934741
+1 W reg=2 val=005A pc=3FA79110 cyc=43934780
+1 W reg=2 val=007A pc=3FA74E60 cyc=43995061
+1 W reg=2 val=0050 pc=3FA74F10 cyc=43995384
+1 W reg=2 val=003A pc=3FA71F20 cyc=43995432
+1 W reg=2 val=002A pc=3FA71FD0 cyc=43995755
+1 W reg=2 val=004A pc=3FA72080 cyc=43996078
+1 W reg=2 val=001A pc=3FA72120 cyc=43996400
+1 W reg=1 val=0088 pc=3FA72220 cyc=43996730
+1 W reg=0 val=0013 pc=3FA73090 cyc=44001284
+1 W reg=0 val=0080 pc=3FA731B0 cyc=44001621
+1 W reg=2 val=0005 pc=3FA73260 cyc=44061742
+1 R reg=5 val=0009 pc=3FA78E30 cyc=44061824
+1 R reg=1 val=000C pc=3FA79E50 cyc=44061905
+1 W reg=3 val=00AA pc=3FA79F00 cyc=44061927
+1 R reg=1 val=0000 pc=3FA79FB0 cyc=44061949
+1 W reg=E val=0000 pc=3FA7A060 cyc=44061971
+1 W reg=F val=0000 pc=3FA7A110 cyc=44061993
+1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44062015
+1 R reg=D val=00F0 pc=3FA7A320 cyc=44062049
+1 R reg=5 val=0009 pc=3FA78E30 cyc=44067214
+1 R reg=1 val=0004 pc=3FA79E50 cyc=44067295
+1 W reg=3 val=00FF pc=3FA79F00 cyc=44067317
+1 R reg=1 val=0000 pc=3FA79FB0 cyc=44067339
+1 W reg=E val=0000 pc=3FA7A060 cyc=44067361
+1 W reg=F val=0000 pc=3FA7A110 cyc=44067383
+1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44067405
+1 R reg=D val=00F0 pc=3FA7A320 cyc=44067439
+1 R reg=5 val=0009 pc=3FA78E30 cyc=44088048
+1 R reg=1 val=0004 pc=3FA79E50 cyc=44088129
+1 W reg=3 val=00AA pc=3FA79F00 cyc=44088151
+1 R reg=1 val=0000 pc=3FA79FB0 cyc=44088173
+1 W reg=E val=0000 pc=3FA7A060 cyc=44088195
+1 W reg=F val=0000 pc=3FA7A110 cyc=44088217
+1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44088239
+1 R reg=D val=00F0 pc=3FA7A320 cyc=44088273
+1 R reg=5 val=000A pc=3FA78E30 cyc=44089350
+1 R reg=1 val=0001 pc=3FA796D0 cyc=44089432
+1 R reg=3 val=00AA pc=3FA79780 cyc=44089454
+1 R reg=1 val=0000 pc=3FA79830 cyc=44089476
+1 R reg=D val=00F0 pc=3FA798E0 cyc=44089498
+1 R reg=D val=00F0 pc=3FA79A20 cyc=44089532
+1 R reg=5 val=0009 pc=3FA78E30 cyc=44114090
+1 R reg=1 val=0004 pc=3FA79E50 cyc=44114171
+1 W reg=3 val=0055 pc=3FA79F00 cyc=44114193
+1 R reg=1 val=0000 pc=3FA79FB0 cyc=44114215
+1 W reg=E val=0000 pc=3FA7A060 cyc=44114237
+1 W reg=F val=0000 pc=3FA7A110 cyc=44114259
+1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44114281
+1 R reg=D val=00F0 pc=3FA7A320 cyc=44114315
+1 R reg=5 val=000A pc=3FA78E30 cyc=44115392
+1 R reg=1 val=0001 pc=3FA796D0 cyc=44115474
+1 R reg=3 val=00FF pc=3FA79780 cyc=44115496
+1 R reg=1 val=0000 pc=3FA79830 cyc=44115518
+1 R reg=D val=00F0 pc=3FA798E0 cyc=44115540
+1 R reg=D val=00F0 pc=3FA79A20 cyc=44115574
+1 R reg=5 val=0009 pc=3FA78E30 cyc=44140131
+1 R reg=1 val=0004 pc=3FA79E50 cyc=44140212
+1 W reg=3 val=0000 pc=3FA79F00 cyc=44140234
+1 R reg=1 val=0000 pc=3FA79FB0 cyc=44140256
+1 W reg=E val=0000 pc=3FA7A060 cyc=44140278
+1 W reg=F val=0000 pc=3FA7A110 cyc=44140300
+1 R reg=D val=00F0 pc=3FA7A1C0 cyc=44140322
+1 R reg=D val=00F0 pc=3FA7A320 cyc=44140356
+1 R reg=5 val=000A pc=3FA78E30 cyc=44141433
+1 R reg=1 val=0001 pc=3FA796D0 cyc=44141515
+1 R reg=3 val=00AA pc=3FA79780 cyc=44141537
+1 R reg=1 val=0000 pc=3FA79830 cyc=44141559
+1 R reg=D val=00F0 pc=3FA798E0 cyc=44141581
+1 R reg=D val=00F0 pc=3FA79A20 cyc=44141615
+1 R reg=5 val=0009 pc=3FA78E30 cyc=44166172
+1 R reg=1 val=0004 pc=3FA7A3C0 cyc=44166242
+1 W reg=2 val=0008 pc=3FA7A3F0 cyc=44166248
+1 R reg=1 val=0000 pc=3FA7A440 cyc=44166256
+1 R reg=5 val=000A pc=3FA78E30 cyc=44167474
+1 R reg=1 val=0001 pc=3FA796D0 cyc=44167556
+1 R reg=3 val=0055 pc=3FA79780 cyc=44167578
+1 R reg=1 val=0000 pc=3FA79830 cyc=44167600
+1 R reg=D val=00F0 pc=3FA798E0 cyc=44167622
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harness/mame/hp_lat2.log

@@ -0,0 +1,443 @@
+# win kind reg val pc -- every DUART access (not de-duplicated)
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