9 Commits

Include renames

Author	SHA1	Message	Date
SDD	14f78f3cbe	plan: the network provider must be selected per device (interface=-1 is none); index 0 = taptun on this build; NVRAM must not be isolated	2026-10-16 16:56:24 +03:00
SDD	7f0b2ff27c	plan: record host-side tap/bridge plumbing for the LANCE network milestone (MAME's tap is tap-mess-<uid>-0, not tap0)	2026-10-16 16:17:43 +03:00
SDD	d017953d52	docs: plan the LANCE Ethernet model + network font delivery ... Evidence for the RAP/RDP window pair (0x5900000/0x5800000), INT1 as the LANCE interrupt, and the separate MAC address ROM at 0x6800000; MAME am79c90 drop-in assessment with the kn01/ncd68k templates; the TFTP/LAT font delivery path (no X font server on 7100); acceptance, risks and sequencing.	2026-10-16 14:16:05 +03:00
SDD	ac60ad2f89	docs: plan to retire the settled VT1200_* env gates (promote working config to default, delete finished experiments)	2026-10-16 13:02:20 +03:00
SDD	1c0a9b2b64	docs: Ghidra decompiler unreliable for this ROM (~85% of sampled functions flagged); SLEIGH instruction coverage incomplete	2026-10-16 11:08:46 +03:00
SDD	49378827e8	fix(tms34010): drop addr32 &0xFFFFF, fix ADDI imm; rebuild .sla, repair program, validate 31691 sites	2026-10-16 10:59:40 +03:00
SDD	f46b4a44a4	docs: root-cause Ghidra TMS34010 CALLA bug to addr32 & 0xFFFFF (empty call graph)	2026-10-16 10:48:02 +03:00
SDD	66784de1aa	docs: memory-space map from the spike; commit the plan amendment; ignore harness logs	2026-10-16 02:15:13 +03:00
SDD	acb92d3e44	checkpoint: VT1200 reverse-engineering workspace before board-model work	2026-10-16 01:37:50 +03:00