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https://git.k-space.ee/arti/vt1200.git
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arti
1d8656ca10
vram_blit_ copies a 1-bpp rectangle from RAM to VRAM. The manual has no L,L variant, so the destination is XY and the hardware forms the address: B0=SADDR B1=SPTCH B2=DADDR(XY) B3=DPTCH=0x800 B4=OFFSET=0x04000000 B7=DYDX PSIZE=1 PMASK=0 CONVSP=CONVDP=0x14 CONTROL raster-op=0 SPTCH is a parameter because 0 makes every row read the same source address, which is how one expanded row can be stamped eight times down the screen. The .bss region in the linker command grows from 0x40000 to 0x200000 address units (32 KB -> 256 KB) so a 1280x1024 1-bpp frame buffer (163840 B) fits; the previous .coff had been built from sources that were not yet committed. bench-sweep.sh gains its executable bit.
113 lines
3.6 KiB
NASM
113 lines
3.6 KiB
NASM
; vram.asm -- hardware framebuffer fill for the VT1200 payload.
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;
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; The C loop in lance_cmd.c writes the screen one byte at a time and measures
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; ~2.0 s per 1280x1024 frame (0.5 fps). FILL L does the same job in the GSP's
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; array engine: the manual's Table 13-6 gives (1 + N*G)L states for a long row,
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; with G=2 for "replace, no plane masking", N=80 words/row and L=1024 rows --
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; about 165k states, i.e. ~16 ms at a 10 MHz state, roughly 120x faster.
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;
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; Implied operands of FILL L (TMS34010 User's Guide, instruction reference):
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; DADDR = B2 linear address of the first pixel of the array
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; DPTCH = B3 pitch between rows, in bits
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; DYDX = B7 dimensions in XY form: (rows << 16) | columns
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; COLOR1 = B9 fill colour / 16-bit pattern
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; CONTROL (0C00000B0h) bits 10-14 PPOP = 0 -> replace (S -> D)
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; PSIZE (0C0000150h) 1 -> one bit per pixel
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; PMASK (0C0000160h) 0 -> no plane protected, all bits writable
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;
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; DADDR and DYDX are modified by the instruction, so they are reloaded on every
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; call. The pattern is read from the C global _vram_pattern (a .bss word) so
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; no calling-convention assumption is needed.
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.ref _vram_pattern
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.text
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.globl _vram_fill_
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_vram_fill_:
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setf 32, 0, 1
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move b2, -*sp, 1
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move b3, -*sp, 1
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move b7, -*sp, 1
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move b9, -*sp, 1
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; --- destination array -------------------------------------------------
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movi 04000000h, b2 ; VRAM base, bit address
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movi 800h, b3 ; 2048 bits = 256-byte row pitch
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movi 04000500h, b7 ; DY=1024 (0400h), DX=1280 (0500h)
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move @_vram_pattern, b9, 1 ; fill pattern
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; --- pixel format ------------------------------------------------------
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movi 1, a1
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move a1, @0C0000150h, 0 ; PSIZE = 1
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clr a1
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move a1, @0C0000160h, 0 ; PMASK = 0 (all planes writable)
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move a1, @0C0000170h, 0 ; upper half, for forward compatibility
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; --- graphics operation: replace, no transparency, no window ----------
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move @0C00000B0h, a1, 0 ; CONTROL
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andi 0801Fh, a1 ; keep CD (15) and RM/RR (2-4) only
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move a1, @0C00000B0h, 0
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move @0C00000B0h, a1, 0 ; read back: I/O writes are pipelined
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fill l
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move *sp+, b9, 1
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move *sp+, b7, 1
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move *sp+, b3, 1
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move *sp+, b2, 1
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rets
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; vram_blit_ -- copy a 1-bpp rectangle from RAM to VRAM with PIXBLT L,XY.
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; The manual has no L,L variant; the destination is XY so the hardware forms
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; the address from OFFSET + y*CONVDP + x (rom:07ee9db6 does the same with
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; MOVI 0x4000000,B4).
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;
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; _blit_src linear source address (bit address, 1 bpp, SPTCH apart)
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; _blit_sptch source pitch in bits; 0 makes every row read the same address
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; _blit_daddr destination XY: (y << 16) | x
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; _blit_dydx dimensions XY: (rows << 16) | columns
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.globl _vram_blit_
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.ref _blit_src
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.ref _blit_sptch
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.ref _blit_daddr
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.ref _blit_dydx
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_vram_blit_:
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setf 32, 0, 1
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move b0, -*sp, 1
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move b1, -*sp, 1
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move b2, -*sp, 1
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move b3, -*sp, 1
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move b4, -*sp, 1
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move b7, -*sp, 1
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move @_blit_src, b0, 1 ; SADDR
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move @_blit_sptch, b1, 1 ; SPTCH
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move @_blit_daddr, b2, 1 ; DADDR (XY)
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movi 800h, b3 ; DPTCH = 256 bytes
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movi 04000000h, b4 ; OFFSET = VRAM base
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move @_blit_dydx, b7, 1 ; DYDX (rows, columns)
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movi 1, a1
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move a1, @0C0000150h, 0 ; PSIZE = 1
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movi 14h, a1
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move a1, @0C0000130h, 0 ; CONVSP = pitch code for 0x800 bits
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move a1, @0C0000140h, 0 ; CONVDP
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clr a1
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move a1, @0C0000160h, 0 ; PMASK = 0
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move a1, @0C0000170h, 0
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move @0C00000B0h, a1, 0 ; CONTROL: keep CD/RM/RR, raster op = 0
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andi 0801Fh, a1
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move a1, @0C00000B0h, 0
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move @0C00000B0h, a1, 0 ; read back (pipelined I/O)
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pixblt l, xy
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move *sp+, b7, 1
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move *sp+, b4, 1
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move *sp+, b3, 1
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move *sp+, b2, 1
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move *sp+, b1, 1
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move *sp+, b0, 1
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rets
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.end
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