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SDD
70e2486d57
Independent verification (reference/mc68681-datasheet-verification.md) read the SCN2681 spec: p.22 "Transmitter Disable Note" -- "TxRDY sets at the end of the 'start bit' time. It is during the start bit that the data in the transmit holding register is transferred to the transmit shift register." That is exactly upstream's tra_callback() assertion, so upstream was faithful and our edit contradicted the datasheet. Reverted; the revert note records the refutation and says not to re-apply. Commit 9902722165fc's "fix two DUART timing deviations" is therefore half false -- only the overrun edit stands. Reverting it does NOT relocate the failure: cfg2 (edit1 off, edit2 on) gives L3FA71BC0=0x00900040, L3FA753D0=3, L3FA767E0=0, L3FA6E4B0=6, console unchanged. "ISR one byte ahead" explained: TxRDY re-asserts at the end of the start bit (faithful), so the ISR writes the next byte ~1 bit into the current character, while MAME clocks the loopback receiver from the independent receive clock -- the datasheet (p.12, local loopback item 2) says "The transmit clock is used for the receiver". Edit 1 was masking that deviation. Next fix identified but not written (needs the quoted sentence read independently first, per process). Step-5 leads: crystal 3.6864 MHz is the datasheet nominal but the board crystal is still unconfirmed; CSRA=0x88 gives TX==RX==2400 baud (the rx arg is unused in calc_baud); MR1A=0x10 -> 5-bit frame matches the 0x1F mask; COUNTER_READY cleared (firmware's own Start-Counter read, not in IMR, not handled); INT1/INT2 immaterial (L3FA78D90 ignores the mask arg; OPCR/OPR cleared, so the single INTRN is the path). Regression holds.