arti/vt1200
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b6f193262a93d04409e7f0a1fd86a221b98c9f13
vt1200/harness
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arti b6f193262a udpstream: drop the old white-box ok/tx-done indicators 
They were drawn at y=850, overlapping the REST text row (846-867), which is
what shows as a stray box over REST in the unit photo. The text panel already
reports OK as YES/NO.
2026-10-30 16:02:40 +02:00
..
c-hello
c-hello: first C program on the VT1200, running on real hardware
2026-10-29 18:25:38 +02:00
dis
checkpoint: VT1200 reverse-engineering workspace before board-model work
2026-10-16 01:37:50 +03:00
hello-world
hello-world: the TMS34010 SDK assembles code that runs on the emulated VT1200
2026-10-18 01:20:38 +03:00
mame
udpstream: drop the old white-box ok/tx-done indicators
2026-10-30 16:02:40 +02:00
sdk-roundtrip
dis34: print long relative JR as jr and surface B-file SP as b15
2026-10-18 00:54:34 +03:00
sdk-scratch
reference: TMS34010 SDK investigation; prove GSPA round trip
2026-10-18 00:39:32 +03:00
udpstream
udpstream: drop the old white-box ok/tx-done indicators
2026-10-30 16:02:40 +02:00
BOOTP_REPORT.md
harness/serve.py: optional BOOTP responder (--bootp) so the VT1200 gets an IP at boot
2026-10-16 17:27:00 +03:00
cap-abc.log
checkpoint: VT1200 reverse-engineering workspace before board-model work
2026-10-16 01:37:50 +03:00
cap-all.log
checkpoint: VT1200 reverse-engineering workspace before board-model work
2026-10-16 01:37:50 +03:00
cap-boot.log
checkpoint: VT1200 reverse-engineering workspace before board-model work
2026-10-16 01:37:50 +03:00
cap-decsnf.log
checkpoint: VT1200 reverse-engineering workspace before board-model work
2026-10-16 01:37:50 +03:00
cap-evil.log
checkpoint: VT1200 reverse-engineering workspace before board-model work
2026-10-16 01:37:50 +03:00
cap-probe.log
checkpoint: VT1200 reverse-engineering workspace before board-model work
2026-10-16 01:37:50 +03:00
cap-snf.log
checkpoint: VT1200 reverse-engineering workspace before board-model work
2026-10-16 01:37:50 +03:00
cap-term.log
checkpoint: VT1200 reverse-engineering workspace before board-model work
2026-10-16 01:37:50 +03:00
cap-tftp.log
checkpoint: VT1200 reverse-engineering workspace before board-model work
2026-10-16 01:37:50 +03:00
cap-wide.log
checkpoint: VT1200 reverse-engineering workspace before board-model work
2026-10-16 01:37:50 +03:00
cap.log
checkpoint: VT1200 reverse-engineering workspace before board-model work
2026-10-16 01:37:50 +03:00
net-setup.sh
harness: net-setup.sh -- recreate the tap+bridge the harness needs (they do not survive a reboot)
2026-10-17 14:15:17 +03:00
serve.py
harness/serve.py: optional BOOTP responder (--bootp) so the VT1200 gets an IP at boot
2026-10-16 17:27:00 +03:00
tftp.log
checkpoint: VT1200 reverse-engineering workspace before board-model work
2026-10-16 01:37:50 +03:00