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arti
d99a9cdb6c
Byte stores to VRAM measure 2284 ms per 1280x1024 frame on the real unit (0.44 fps) -- about a scanline period per byte, i.e. almost no access through the arbiter. vram.asm now drives the GSP's array engine instead: FILL L with DADDR/DPTCH/DYDX/COLOR1 (B2/B3/B7/B9), PSIZE=1, PMASK=0 and PPOP=0, per the TMS34010 User's Guide's implied-operand table, with CONTROL read-modify-written so CD/RM/RR survive. Measured: 32.7 ms/frame, 30.6 fps on the unit; 27.1 ms in MAME (74x over byte stores there, 70x on hardware). 2,508,224 destination words/s = 0.40 us/word. Consequence for video: a full uncompressed frame is wire-limited at 8 fps (163840 B at 1.27 MB/s); a small source expanded on the device is limited by the ~33 ms transfer, i.e. ~30 fps full screen if the expansion uses PIXBLT. build-lance.sh assembles vram.asm and links VRAM.obj; MARK moved to 0x01A00000 because .text had come within 146 bytes of it.
60 lines
2.1 KiB
NASM
60 lines
2.1 KiB
NASM
; vram.asm -- hardware framebuffer fill for the VT1200 payload.
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;
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; The C loop in lance_cmd.c writes the screen one byte at a time and measures
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; ~2.0 s per 1280x1024 frame (0.5 fps). FILL L does the same job in the GSP's
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; array engine: the manual's Table 13-6 gives (1 + N*G)L states for a long row,
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; with G=2 for "replace, no plane masking", N=80 words/row and L=1024 rows --
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; about 165k states, i.e. ~16 ms at a 10 MHz state, roughly 120x faster.
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;
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; Implied operands of FILL L (TMS34010 User's Guide, instruction reference):
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; DADDR = B2 linear address of the first pixel of the array
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; DPTCH = B3 pitch between rows, in bits
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; DYDX = B7 dimensions in XY form: (rows << 16) | columns
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; COLOR1 = B9 fill colour / 16-bit pattern
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; CONTROL (0C00000B0h) bits 10-14 PPOP = 0 -> replace (S -> D)
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; PSIZE (0C0000150h) 1 -> one bit per pixel
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; PMASK (0C0000160h) 0 -> no plane protected, all bits writable
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;
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; DADDR and DYDX are modified by the instruction, so they are reloaded on every
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; call. The pattern is read from the C global _vram_pattern (a .bss word) so
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; no calling-convention assumption is needed.
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.ref _vram_pattern
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.text
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.globl _vram_fill_
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_vram_fill_:
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setf 32, 0, 1
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move b2, -*sp, 1
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move b3, -*sp, 1
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move b7, -*sp, 1
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move b9, -*sp, 1
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; --- destination array -------------------------------------------------
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movi 04000000h, b2 ; VRAM base, bit address
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movi 800h, b3 ; 2048 bits = 256-byte row pitch
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movi 04000500h, b7 ; DY=1024 (0400h), DX=1280 (0500h)
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move @_vram_pattern, b9, 1 ; fill pattern
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; --- pixel format ------------------------------------------------------
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movi 1, a1
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move a1, @0C0000150h, 0 ; PSIZE = 1
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clr a1
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move a1, @0C0000160h, 0 ; PMASK = 0 (all planes writable)
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move a1, @0C0000170h, 0 ; upper half, for forward compatibility
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; --- graphics operation: replace, no transparency, no window ----------
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move @0C00000B0h, a1, 0 ; CONTROL
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andi 0801Fh, a1 ; keep CD (15) and RM/RR (2-4) only
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move a1, @0C00000B0h, 0
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move @0C00000B0h, a1, 0 ; read back: I/O writes are pipelined
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fill l
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move *sp+, b9, 1
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move *sp+, b7, 1
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move *sp+, b3, 1
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move *sp+, b2, 1
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rets
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.end
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