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opencode.energia.arti.ee/vt1200
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216 Commits 1 Branch 0 Tags
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5 Commits
Author SHA1 Message Date
SDD 5ed4048720 gitignore: ignore root RAM dumps (ROM stays tracked) and the Ghidra transient lock; untrack the lock file 2026-10-16 17:11:29 +03:00
SDD 5000b8bc07 harness: level-1 VIDEO MEMORY test passes (video RAM mapped + REFCNT advances); next gate is HOST PORT 2026-10-16 10:57:06 +03:00
SDD 8a00cef556 docs: Ghidra CALLA targets do not resolve (empty call graph); smart34010 is authoritative for call targets 2026-10-16 10:38:16 +03:00
SDD 66784de1aa docs: memory-space map from the spike; commit the plan amendment; ignore harness logs 2026-10-16 02:15:13 +03:00
SDD acb92d3e44 checkpoint: VT1200 reverse-engineering workspace before board-model work 2026-10-16 01:37:50 +03:00
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