tms34010: add MOVE/MOVB load-store codegen

llvm/lib/Target/TMS34010/TMS34010ISelLowering.cpp

@@ -22,6 +22,11 @@ TMS34010TargetLowering::TMS34010TargetLowering(const TargetMachine &TM,
     : TargetLowering(TM, STI) {
   addRegisterClass(MVT::i32, &TMS34010::ARegsRegClass);
 
+  // MOVB is an 8-bit sign-extending load and an 8-bit truncating store.
+  // M1 only needs signed char, so a zero-extending byte load has no pattern.
+  setLoadExtAction(ISD::SEXTLOAD, MVT::i32, MVT::i8, Legal);
+  setTruncStoreAction(MVT::i32, MVT::i8, Legal);
+
   computeRegisterProperties(STI.getRegisterInfo());
 
   setBooleanContents(ZeroOrOneBooleanContent);

llvm/lib/Target/TMS34010/TMS34010InstrInfo.td

@@ -74,6 +74,62 @@ def MOVE : TMS34010Inst<(outs ARegs:$dst), (ins ARegs:$src),
   let Inst{4-0} = dst;
 }
 
+// Memory forms use bits 15-10 as the addressing-mode opcode, bits 8-5 as
+// the source register number, bit 4 as the register file, and bits 3-0 as
+// the destination register number.  For MOVE, bit 9 selects FS0 (16-bit)
+// or FS1 (32-bit); for MOVB, bit 9 is part of the opcode.
+// MOVE *Rs, Rd, FS1: 32-bit load.  1000 011S SSSF DDDD (0x8600)
+def MOVE32Load : TMS34010Inst<(outs ARegs:$dst), (ins ARegs:$src),
+                              "MOVE *$src, $dst, 1",
+                              [(set ARegs:$dst, (load ARegs:$src))]> {
+  let mayLoad = 1;
+  bits<5> src;
+  bits<5> dst;
+  let Inst{15-9} = 0b1000011;
+  let Inst{8-5} = src{3-0};
+  let Inst{4} = src{4};
+  let Inst{3-0} = dst{3-0};
+}
+
+// MOVE Rs, *Rd, FS1: 32-bit store.  1000 001S SSSF DDDD (0x8200)
+def MOVE32Store : TMS34010Inst<(outs), (ins ARegs:$src, ARegs:$dst),
+                               "MOVE $src, *$dst, 1",
+                               [(store ARegs:$src, ARegs:$dst)]> {
+  let mayStore = 1;
+  bits<5> src;
+  bits<5> dst;
+  let Inst{15-9} = 0b1000001;
+  let Inst{8-5} = src{3-0};
+  let Inst{4} = dst{4};
+  let Inst{3-0} = dst{3-0};
+}
+
+// MOVB *Rs, Rd: 8-bit sign-extending load.  1000 111S SSSF DDDD (0x8e00)
+def MOVBLoad : TMS34010Inst<(outs ARegs:$dst), (ins ARegs:$src),
+                            "MOVB *$src, $dst",
+                            [(set ARegs:$dst, (sextloadi8 ARegs:$src))]> {
+  let mayLoad = 1;
+  bits<5> src;
+  bits<5> dst;
+  let Inst{15-9} = 0b1000111;
+  let Inst{8-5} = src{3-0};
+  let Inst{4} = src{4};
+  let Inst{3-0} = dst{3-0};
+}
+
+// MOVB Rs, *Rd: 8-bit truncating store.  1000 110S SSSF DDDD (0x8c00)
+def MOVBStore : TMS34010Inst<(outs), (ins ARegs:$src, ARegs:$dst),
+                             "MOVB $src, *$dst",
+                             [(truncstorei8 ARegs:$src, ARegs:$dst)]> {
+  let mayStore = 1;
+  bits<5> src;
+  bits<5> dst;
+  let Inst{15-9} = 0b1000110;
+  let Inst{8-5} = src{3-0};
+  let Inst{4} = dst{4};
+  let Inst{3-0} = dst{3-0};
+}
+
 // CLR Rd: XOR self, base 0x5600 (0101 011S SSSR DDDD with S == D).
 def CLR : TMS34010Inst<(outs ARegs:$dst), (ins), "CLR $dst", []> {
   bits<5> dst;

llvm/test/CodeGen/TMS34010/m1-char.ll

@@ -0,0 +1,15 @@
+; RUN: llc -march=tms34010 -O2 -filetype=asm < %s | FileCheck %s
+define i32 @loadb(ptr %p) {
+  %v = load i8, ptr %p
+  %r = sext i8 %v to i32
+  ret i32 %r
+}
+define void @storeb(ptr %p, i32 %v) {
+  %t = trunc i32 %v to i8
+  store i8 %t, ptr %p
+  ret void
+}
+; CHECK-LABEL: _loadb:
+; CHECK: MOVB *A{{[0-9]+}}, A{{[0-9]+}}
+; CHECK-LABEL: _storeb:
+; CHECK: MOVB A{{[0-9]+}}, *A{{[0-9]+}}

llvm/test/CodeGen/TMS34010/m1-load.ll

@@ -0,0 +1,8 @@
+; RUN: llc -march=tms34010 -O2 -filetype=asm < %s | FileCheck %s
+define i32 @load(ptr %p) {
+  %v = load i32, ptr %p
+  ret i32 %v
+}
+; CHECK-LABEL: _load:
+; CHECK: MOVE *A{{[0-9]+}}, A{{[0-9]+}}, 1
+; CHECK: RETS 0