[VPlan] Don't merge allocas across lanes, parts or recipes. (#229929)
Each execution of an alloca creates a new allocation, distinct from the allocations of all other executions. They must not be merged, either by CSE or via isUniformAcrossVFsAndUFs. Update those to explicitly handle Alloca recipes. Fixes https://github.com/llvm/llvm-project/issues/229389. PR: https://github.com/llvm/llvm-project/pull/229929 (cherry picked from commit 95ea23b7d5b06c60c513c575577d5b7d0ed15721)
This commit is contained in:
Florian Hahn authored and 
Douglas Yung committed
1 parent
86fe084e4c
commit
b10c62b2d9
5 files changed
+89
-32
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@@ -2542,9 +2542,10 @@ struct VPCSEDenseMapInfo : public DenseMapInfo<VPSingleDefRecipe *> {
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// The issue with (Insert|Extract)Value is that the index of the
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// insert/extract is not a proper operand in LLVM IR, and hence also not in
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// VPlan.
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// VPlan. Allocas must not be merged, as each creates a distinct allocation.
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if (!C || (!C->first && (C->second == Instruction::InsertValue ||
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C->second == Instruction::ExtractValue)))
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C->second == Instruction::ExtractValue ||
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C->second == Instruction::Alloca)))
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return false;
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// During CSE, we can only handle non-memory recipes, as memory can alias.
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@@ -486,8 +486,9 @@ bool vputils::isUniformAcrossVFsAndUFs(const VPValue *V) {
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.Case([](const VPReplicateRecipe *R) {
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// Be conservative about side-effects, except for the
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// known-side-effecting assumes and stores, which we know will be
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// uniform.
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return R->isSingleScalar() &&
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// uniform. Each alloca creates a distinct allocation, so allocas are
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// never uniform.
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return R->isSingleScalar() && R->getOpcode() != Instruction::Alloca &&
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(!R->mayHaveSideEffects() ||
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isa<AssumeInst, StoreInst>(R->getUnderlyingInstr())) &&
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all_of(R->operands(), isUniformAcrossVFsAndUFs);
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@@ -325,12 +325,17 @@ define void @invalid_legacy_cost(i64 %N, ptr %x) #0 {
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; COST1: [[VECTOR_BODY]]:
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; COST1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; COST1-NEXT: [[TMP1:%.*]] = alloca i8, i64 0, align 16
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; COST1-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x ptr> poison, ptr [[TMP1]], i64 0
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; COST1-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x ptr> [[BROADCAST_SPLATINSERT]], <2 x ptr> poison, <2 x i32> zeroinitializer
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; COST1-NEXT: [[TMP10:%.*]] = alloca i8, i64 0, align 16
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; COST1-NEXT: [[TMP11:%.*]] = insertelement <2 x ptr> poison, ptr [[TMP1]], i64 0
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; COST1-NEXT: [[TMP5:%.*]] = insertelement <2 x ptr> [[TMP11]], ptr [[TMP10]], i64 1
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; COST1-NEXT: [[TMP6:%.*]] = alloca i8, i64 0, align 16
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; COST1-NEXT: [[TMP7:%.*]] = alloca i8, i64 0, align 16
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; COST1-NEXT: [[TMP8:%.*]] = insertelement <2 x ptr> poison, ptr [[TMP6]], i64 0
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; COST1-NEXT: [[TMP9:%.*]] = insertelement <2 x ptr> [[TMP8]], ptr [[TMP7]], i64 1
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; COST1-NEXT: [[TMP2:%.*]] = getelementptr ptr, ptr [[X]], i64 [[INDEX]]
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; COST1-NEXT: [[TMP3:%.*]] = getelementptr ptr, ptr [[TMP2]], i64 2
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; COST1-NEXT: store <2 x ptr> [[BROADCAST_SPLAT]], ptr [[TMP2]], align 8
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; COST1-NEXT: store <2 x ptr> [[BROADCAST_SPLAT]], ptr [[TMP3]], align 8
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; COST1-NEXT: store <2 x ptr> [[TMP5]], ptr [[TMP2]], align 8
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; COST1-NEXT: store <2 x ptr> [[TMP9]], ptr [[TMP3]], align 8
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; COST1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
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; COST1-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; COST1-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
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@@ -352,10 +357,11 @@ define void @invalid_legacy_cost(i64 %N, ptr %x) #0 {
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; COST10: [[VECTOR_BODY]]:
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; COST10-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; COST10-NEXT: [[TMP1:%.*]] = alloca i8, i64 0, align 16
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; COST10-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x ptr> poison, ptr [[TMP1]], i64 0
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; COST10-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x ptr> [[BROADCAST_SPLATINSERT]], <2 x ptr> poison, <2 x i32> zeroinitializer
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; COST10-NEXT: [[TMP6:%.*]] = alloca i8, i64 0, align 16
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; COST10-NEXT: [[TMP4:%.*]] = insertelement <2 x ptr> poison, ptr [[TMP1]], i64 0
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; COST10-NEXT: [[TMP5:%.*]] = insertelement <2 x ptr> [[TMP4]], ptr [[TMP6]], i64 1
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; COST10-NEXT: [[TMP2:%.*]] = getelementptr ptr, ptr [[X]], i64 [[INDEX]]
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; COST10-NEXT: store <2 x ptr> [[BROADCAST_SPLAT]], ptr [[TMP2]], align 8
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; COST10-NEXT: store <2 x ptr> [[TMP5]], ptr [[TMP2]], align 8
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; COST10-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
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; COST10-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; COST10-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
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@@ -27,20 +27,33 @@ define void @alloca_address_stored(ptr noalias %dst, i64 %n) {
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; VF4IC2-NEXT: [[TMP7:%.*]] = add i32 [[TMP1]], 6
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; VF4IC2-NEXT: [[TMP8:%.*]] = add i32 [[TMP1]], 7
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; VF4IC2-NEXT: [[TMP9:%.*]] = alloca [8 x i8], align 16
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; VF4IC2-NEXT: [[TMP13:%.*]] = alloca [8 x i8], align 16
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; VF4IC2-NEXT: [[TMP16:%.*]] = alloca [8 x i8], align 16
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; VF4IC2-NEXT: [[TMP25:%.*]] = alloca [8 x i8], align 16
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; VF4IC2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x ptr> poison, ptr [[TMP9]], i64 0
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; VF4IC2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x ptr> [[BROADCAST_SPLATINSERT]], <4 x ptr> poison, <4 x i32> zeroinitializer
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; VF4IC2-NEXT: [[TMP14:%.*]] = insertelement <4 x ptr> [[BROADCAST_SPLATINSERT]], ptr [[TMP13]], i64 1
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; VF4IC2-NEXT: [[TMP15:%.*]] = insertelement <4 x ptr> [[TMP14]], ptr [[TMP16]], i64 2
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; VF4IC2-NEXT: [[BROADCAST_SPLAT:%.*]] = insertelement <4 x ptr> [[TMP15]], ptr [[TMP25]], i64 3
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; VF4IC2-NEXT: [[TMP17:%.*]] = alloca [8 x i8], align 16
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; VF4IC2-NEXT: [[TMP18:%.*]] = alloca [8 x i8], align 16
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; VF4IC2-NEXT: [[TMP19:%.*]] = alloca [8 x i8], align 16
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; VF4IC2-NEXT: [[TMP20:%.*]] = alloca [8 x i8], align 16
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; VF4IC2-NEXT: [[TMP21:%.*]] = insertelement <4 x ptr> poison, ptr [[TMP17]], i64 0
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; VF4IC2-NEXT: [[TMP22:%.*]] = insertelement <4 x ptr> [[TMP21]], ptr [[TMP18]], i64 1
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; VF4IC2-NEXT: [[TMP23:%.*]] = insertelement <4 x ptr> [[TMP22]], ptr [[TMP19]], i64 2
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; VF4IC2-NEXT: [[TMP24:%.*]] = insertelement <4 x ptr> [[TMP23]], ptr [[TMP20]], i64 3
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; VF4IC2-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[DST]], i64 [[INDEX]]
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; VF4IC2-NEXT: [[TMP11:%.*]] = getelementptr inbounds ptr, ptr [[TMP10]], i64 4
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; VF4IC2-NEXT: store <4 x ptr> [[BROADCAST_SPLAT]], ptr [[TMP10]], align 8
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; VF4IC2-NEXT: store <4 x ptr> [[BROADCAST_SPLAT]], ptr [[TMP11]], align 8
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; VF4IC2-NEXT: store <4 x ptr> [[TMP24]], ptr [[TMP11]], align 8
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; VF4IC2-NEXT: store i32 [[TMP1]], ptr [[TMP9]], align 4
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; VF4IC2-NEXT: store i32 [[TMP2]], ptr [[TMP9]], align 4
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; VF4IC2-NEXT: store i32 [[TMP3]], ptr [[TMP9]], align 4
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; VF4IC2-NEXT: store i32 [[TMP4]], ptr [[TMP9]], align 4
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; VF4IC2-NEXT: store i32 [[TMP5]], ptr [[TMP9]], align 4
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; VF4IC2-NEXT: store i32 [[TMP6]], ptr [[TMP9]], align 4
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; VF4IC2-NEXT: store i32 [[TMP7]], ptr [[TMP9]], align 4
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; VF4IC2-NEXT: store i32 [[TMP8]], ptr [[TMP9]], align 4
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; VF4IC2-NEXT: store i32 [[TMP2]], ptr [[TMP13]], align 4
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; VF4IC2-NEXT: store i32 [[TMP3]], ptr [[TMP16]], align 4
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; VF4IC2-NEXT: store i32 [[TMP4]], ptr [[TMP25]], align 4
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; VF4IC2-NEXT: store i32 [[TMP5]], ptr [[TMP17]], align 4
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; VF4IC2-NEXT: store i32 [[TMP6]], ptr [[TMP18]], align 4
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; VF4IC2-NEXT: store i32 [[TMP7]], ptr [[TMP19]], align 4
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; VF4IC2-NEXT: store i32 [[TMP8]], ptr [[TMP20]], align 4
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; VF4IC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
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; VF4IC2-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; VF4IC2-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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@@ -64,12 +77,13 @@ define void @alloca_address_stored(ptr noalias %dst, i64 %n) {
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; VF1IC2-NEXT: [[TMP2:%.*]] = trunc i64 [[INDEX]] to i32
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; VF1IC2-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], 1
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; VF1IC2-NEXT: [[TMP4:%.*]] = alloca [8 x i8], align 16
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; VF1IC2-NEXT: [[TMP8:%.*]] = alloca [8 x i8], align 16
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; VF1IC2-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[DST]], i64 [[INDEX]]
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; VF1IC2-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[DST]], i64 [[TMP1]]
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; VF1IC2-NEXT: store ptr [[TMP4]], ptr [[TMP5]], align 8
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; VF1IC2-NEXT: store ptr [[TMP4]], ptr [[TMP6]], align 8
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; VF1IC2-NEXT: store ptr [[TMP8]], ptr [[TMP6]], align 8
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; VF1IC2-NEXT: store i32 [[TMP2]], ptr [[TMP4]], align 4
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; VF1IC2-NEXT: store i32 [[TMP3]], ptr [[TMP4]], align 4
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; VF1IC2-NEXT: store i32 [[TMP3]], ptr [[TMP8]], align 4
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; VF1IC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
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; VF1IC2-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; VF1IC2-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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@@ -111,16 +125,45 @@ define void @two_allocas_different_types(ptr noalias %dst.a, ptr noalias %dst.b,
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; VF4IC2: [[VECTOR_BODY]]:
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; VF4IC2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; VF4IC2-NEXT: [[TMP1:%.*]] = alloca i32, align 4
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; VF4IC2-NEXT: [[TMP8:%.*]] = alloca i32, align 4
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; VF4IC2-NEXT: [[TMP33:%.*]] = alloca i32, align 4
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; VF4IC2-NEXT: [[TMP34:%.*]] = alloca i32, align 4
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; VF4IC2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x ptr> poison, ptr [[TMP1]], i64 0
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; VF4IC2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x ptr> [[BROADCAST_SPLATINSERT]], <4 x ptr> poison, <4 x i32> zeroinitializer
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; VF4IC2-NEXT: [[TMP35:%.*]] = insertelement <4 x ptr> [[BROADCAST_SPLATINSERT]], ptr [[TMP8]], i64 1
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; VF4IC2-NEXT: [[TMP7:%.*]] = insertelement <4 x ptr> [[TMP35]], ptr [[TMP33]], i64 2
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; VF4IC2-NEXT: [[BROADCAST_SPLAT:%.*]] = insertelement <4 x ptr> [[TMP7]], ptr [[TMP34]], i64 3
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; VF4IC2-NEXT: [[TMP9:%.*]] = alloca i32, align 4
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; VF4IC2-NEXT: [[TMP10:%.*]] = alloca i32, align 4
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; VF4IC2-NEXT: [[TMP11:%.*]] = alloca i32, align 4
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; VF4IC2-NEXT: [[TMP12:%.*]] = alloca i32, align 4
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; VF4IC2-NEXT: [[TMP13:%.*]] = insertelement <4 x ptr> poison, ptr [[TMP9]], i64 0
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; VF4IC2-NEXT: [[TMP14:%.*]] = insertelement <4 x ptr> [[TMP13]], ptr [[TMP10]], i64 1
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; VF4IC2-NEXT: [[TMP15:%.*]] = insertelement <4 x ptr> [[TMP14]], ptr [[TMP11]], i64 2
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; VF4IC2-NEXT: [[TMP16:%.*]] = insertelement <4 x ptr> [[TMP15]], ptr [[TMP12]], i64 3
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; VF4IC2-NEXT: [[TMP17:%.*]] = alloca i64, align 4
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; VF4IC2-NEXT: [[TMP18:%.*]] = alloca i64, align 4
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; VF4IC2-NEXT: [[TMP19:%.*]] = alloca i64, align 4
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; VF4IC2-NEXT: [[TMP20:%.*]] = alloca i64, align 4
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; VF4IC2-NEXT: [[TMP21:%.*]] = insertelement <4 x ptr> poison, ptr [[TMP17]], i64 0
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; VF4IC2-NEXT: [[TMP22:%.*]] = insertelement <4 x ptr> [[TMP21]], ptr [[TMP18]], i64 1
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; VF4IC2-NEXT: [[TMP23:%.*]] = insertelement <4 x ptr> [[TMP22]], ptr [[TMP19]], i64 2
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; VF4IC2-NEXT: [[TMP24:%.*]] = insertelement <4 x ptr> [[TMP23]], ptr [[TMP20]], i64 3
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; VF4IC2-NEXT: [[TMP25:%.*]] = alloca i64, align 4
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; VF4IC2-NEXT: [[TMP26:%.*]] = alloca i64, align 4
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; VF4IC2-NEXT: [[TMP27:%.*]] = alloca i64, align 4
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; VF4IC2-NEXT: [[TMP28:%.*]] = alloca i64, align 4
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; VF4IC2-NEXT: [[TMP29:%.*]] = insertelement <4 x ptr> poison, ptr [[TMP25]], i64 0
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; VF4IC2-NEXT: [[TMP30:%.*]] = insertelement <4 x ptr> [[TMP29]], ptr [[TMP26]], i64 1
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; VF4IC2-NEXT: [[TMP31:%.*]] = insertelement <4 x ptr> [[TMP30]], ptr [[TMP27]], i64 2
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; VF4IC2-NEXT: [[TMP32:%.*]] = insertelement <4 x ptr> [[TMP31]], ptr [[TMP28]], i64 3
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; VF4IC2-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[DST_A]], i64 [[INDEX]]
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; VF4IC2-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP2]], i64 4
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; VF4IC2-NEXT: store <4 x ptr> [[BROADCAST_SPLAT]], ptr [[TMP2]], align 8
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; VF4IC2-NEXT: store <4 x ptr> [[BROADCAST_SPLAT]], ptr [[TMP3]], align 8
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; VF4IC2-NEXT: store <4 x ptr> [[TMP16]], ptr [[TMP3]], align 8
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; VF4IC2-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[DST_B]], i64 [[INDEX]]
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; VF4IC2-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP4]], i64 4
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; VF4IC2-NEXT: store <4 x ptr> [[BROADCAST_SPLAT]], ptr [[TMP4]], align 8
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; VF4IC2-NEXT: store <4 x ptr> [[BROADCAST_SPLAT]], ptr [[TMP5]], align 8
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; VF4IC2-NEXT: store <4 x ptr> [[TMP24]], ptr [[TMP4]], align 8
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; VF4IC2-NEXT: store <4 x ptr> [[TMP32]], ptr [[TMP5]], align 8
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; VF4IC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
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; VF4IC2-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; VF4IC2-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
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@@ -142,14 +185,17 @@ define void @two_allocas_different_types(ptr noalias %dst.a, ptr noalias %dst.b,
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; VF1IC2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; VF1IC2-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1
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; VF1IC2-NEXT: [[TMP2:%.*]] = alloca i32, align 4
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; VF1IC2-NEXT: [[TMP8:%.*]] = alloca i32, align 4
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; VF1IC2-NEXT: [[TMP9:%.*]] = alloca i64, align 4
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; VF1IC2-NEXT: [[TMP10:%.*]] = alloca i64, align 4
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; VF1IC2-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[DST_A]], i64 [[INDEX]]
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; VF1IC2-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[DST_A]], i64 [[TMP1]]
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; VF1IC2-NEXT: store ptr [[TMP2]], ptr [[TMP3]], align 8
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; VF1IC2-NEXT: store ptr [[TMP2]], ptr [[TMP4]], align 8
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; VF1IC2-NEXT: store ptr [[TMP8]], ptr [[TMP4]], align 8
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; VF1IC2-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[DST_B]], i64 [[INDEX]]
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; VF1IC2-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[DST_B]], i64 [[TMP1]]
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; VF1IC2-NEXT: store ptr [[TMP2]], ptr [[TMP5]], align 8
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; VF1IC2-NEXT: store ptr [[TMP2]], ptr [[TMP6]], align 8
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; VF1IC2-NEXT: store ptr [[TMP9]], ptr [[TMP5]], align 8
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; VF1IC2-NEXT: store ptr [[TMP10]], ptr [[TMP6]], align 8
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; VF1IC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
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; VF1IC2-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; VF1IC2-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
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@@ -13,6 +13,9 @@ define i32 @test(ptr %vf1, i64 %n) {
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; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i8> [ <i8 0, i8 1, i8 2, i8 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE6]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = icmp ule <4 x i8> [[VEC_IND]], splat (i8 -56)
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; CHECK-NEXT: [[TMP18:%.*]] = alloca i8, i64 [[N]], align 16
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; CHECK-NEXT: [[TMP2:%.*]] = alloca i8, i64 [[N]], align 16
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; CHECK-NEXT: [[TMP8:%.*]] = alloca i8, i64 [[N]], align 16
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; CHECK-NEXT: [[TMP4:%.*]] = alloca i8, i64 [[N]], align 16
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; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i1> [[TMP0]], i64 0
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; CHECK-NEXT: br i1 [[TMP1]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
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; CHECK: [[PRED_STORE_IF]]:
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@@ -25,7 +28,7 @@ define i32 @test(ptr %vf1, i64 %n) {
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; CHECK: [[PRED_STORE_IF1]]:
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; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 1
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; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[VF1]], i64 [[TMP6]]
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; CHECK-NEXT: store ptr [[TMP18]], ptr [[TMP7]], align 8
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; CHECK-NEXT: store ptr [[TMP2]], ptr [[TMP7]], align 8
|
||||
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE2]]
|
||||
; CHECK: [[PRED_STORE_CONTINUE2]]:
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i1> [[TMP0]], i64 2
|
||||
@@ -33,7 +36,7 @@ define i32 @test(ptr %vf1, i64 %n) {
|
||||
; CHECK: [[PRED_STORE_IF3]]:
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 2
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds ptr, ptr [[VF1]], i64 [[TMP10]]
|
||||
; CHECK-NEXT: store ptr [[TMP18]], ptr [[TMP11]], align 8
|
||||
; CHECK-NEXT: store ptr [[TMP8]], ptr [[TMP11]], align 8
|
||||
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE4]]
|
||||
; CHECK: [[PRED_STORE_CONTINUE4]]:
|
||||
; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x i1> [[TMP0]], i64 3
|
||||
@@ -41,7 +44,7 @@ define i32 @test(ptr %vf1, i64 %n) {
|
||||
; CHECK: [[PRED_STORE_IF5]]:
|
||||
; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 3
|
||||
; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds ptr, ptr [[VF1]], i64 [[TMP14]]
|
||||
; CHECK-NEXT: store ptr [[TMP18]], ptr [[TMP15]], align 8
|
||||
; CHECK-NEXT: store ptr [[TMP4]], ptr [[TMP15]], align 8
|
||||
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE6]]
|
||||
; CHECK: [[PRED_STORE_CONTINUE6]]:
|
||||
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
|
||||
|
||||
Reference in new issue
Block a user