tms34010: add store codegen test and M1 test infra fixes

Test the 32-bit and 16-bit store paths (MOVE ..., 1 / ..., 0) and take
the shared register-file bit from the store data source (src{4}) with
the same-file invariant documented.  Gate the lit directory on the
TMS34010 target being built, and run the no-stack frame test at -O2
with an escaping alloca.

llvm/lib/Target/TMS34010/TMS34010InstrInfo.td

@@ -77,7 +77,10 @@ def MOVE : TMS34010Inst<(outs ARegs:$dst), (ins ARegs:$src),
 // Memory forms use bits 15-10 as the addressing-mode opcode, bits 8-5 as
 // the source register number, bit 4 as the register file, and bits 3-0 as
 // the destination register number.  For MOVE, bit 9 selects FS0 (16-bit)
-// or FS1 (32-bit); for MOVB, bit 9 is part of the opcode.
+// or FS1 (32-bit); for MOVB, bit 9 is part of the opcode.  Bit 4 is shared
+// by both register numbers, so a memory-form source and destination must be
+// in the same register file (both A or both B); store forms therefore take
+// Inst{4} from the data source, src{4}.
 // MOVE *Rs, Rd, FS1: 32-bit load.  1000 011S SSSF DDDD (0x8600)
 def MOVE32Load : TMS34010Inst<(outs ARegs:$dst), (ins ARegs:$src),
                               "MOVE *$src, $dst, 1",
@@ -100,7 +103,7 @@ def MOVE32Store : TMS34010Inst<(outs), (ins ARegs:$src, ARegs:$dst),
   bits<5> dst;
   let Inst{15-9} = 0b1000001;
   let Inst{8-5} = src{3-0};
-  let Inst{4} = dst{4};
+  let Inst{4} = src{4};
   let Inst{3-0} = dst{3-0};
 }
 
@@ -126,7 +129,7 @@ def MOVE16Store : TMS34010Inst<(outs), (ins ARegs:$src, ARegs:$dst),
   bits<5> dst;
   let Inst{15-9} = 0b1000000;
   let Inst{8-5} = src{3-0};
-  let Inst{4} = dst{4};
+  let Inst{4} = src{4};
   let Inst{3-0} = dst{3-0};
 }
 
@@ -152,7 +155,7 @@ def MOVBStore : TMS34010Inst<(outs), (ins ARegs:$src, ARegs:$dst),
   bits<5> dst;
   let Inst{15-9} = 0b1000110;
   let Inst{8-5} = src{3-0};
-  let Inst{4} = dst{4};
+  let Inst{4} = src{4};
   let Inst{3-0} = dst{3-0};
 }
 

llvm/test/CodeGen/TMS34010/lit.local.cfg

@@ -0,0 +1,2 @@
+if not "TMS34010" in config.root.targets:
+    config.unsupported = True

llvm/test/CodeGen/TMS34010/m1-frame.ll

@@ -1,4 +1,9 @@
 ; RUN: not llc -march=tms34010 -O0 -filetype=asm < %s 2>&1 | FileCheck %s
+; RUN: not llc -march=tms34010 -O2 -filetype=asm < %s 2>&1 | FileCheck %s
+;
+; M1 has no stack.  The first function needs a frame at -O0; the escaping
+; alloca below keeps the frame requirement even if the optimizer removes the
+; first one at -O2.
 ; CHECK: M1 has no stack frame
 define i32 @frame(i32 %n) {
   %a = alloca i32
@@ -6,3 +11,9 @@ define i32 @frame(i32 %n) {
   %v = load i32, ptr %a
   ret i32 %v
 }
+
+define ptr @escape(i32 %n) {
+  %a = alloca i32
+  store i32 %n, ptr %a
+  ret ptr %a
+}

llvm/test/CodeGen/TMS34010/m1-store.ll

@@ -0,0 +1,21 @@
+; RUN: llc -march=tms34010 -O2 -filetype=asm < %s | FileCheck %s
+;
+; 32-bit and 16-bit stores must select the memory-form MOVE with the right
+; field select.  The hand-written MAME harness only executes the byte store.
+define void @store32(ptr %p, i32 %v) {
+  store i32 %v, ptr %p
+  ret void
+}
+
+define void @store16(ptr %p, i32 %v) {
+  %t = trunc i32 %v to i16
+  store i16 %t, ptr %p
+  ret void
+}
+
+; CHECK-LABEL: _store32:
+; CHECK: MOVE A{{[0-9]+}}, *A{{[0-9]+}}, 1
+; CHECK: RETS 0
+; CHECK-LABEL: _store16:
+; CHECK: MOVE A{{[0-9]+}}, *A{{[0-9]+}}, 0
+; CHECK: RETS 0