Alexis Engelke
5bc1978405
This moves the large SubTypeKV arrays to .rodata, as they no longer
contain the key pointers that need to be relocated.
Additionally, remove the largely redundant CPUNames arrays and integrate
the AArch64 aliases into the sorted string table. There was really no
need to introduce these 17 kiB arrays solely for including AArch64
aliases in help output.... (added in b6c22a4)
77 lines
2.3 KiB
C++
77 lines
2.3 KiB
C++
//===- TargetSubtargetInfo.cpp - General Target Information ----------------==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file describes the general parts of a Subtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/Intrinsics.h"
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using namespace llvm;
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TargetSubtargetInfo::TargetSubtargetInfo(
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const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
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StringTable PN, ArrayRef<SubtargetFeatureKV> PF,
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ArrayRef<SubtargetSubTypeKV> PD, const MCSchedModel *PSM,
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const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
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const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC,
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const unsigned *FP)
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: MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PSM, WPR, WL, RA, IS,
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OC, FP) {}
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TargetSubtargetInfo::~TargetSubtargetInfo() = default;
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bool TargetSubtargetInfo::isIntrinsicSupported(unsigned IntrinsicID) const {
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StringRef RequiredFeatures = Intrinsic::getRequiredTargetFeatures(
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static_cast<Intrinsic::ID>(IntrinsicID));
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if (RequiredFeatures.empty())
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return true;
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auto [It, Inserted] = IntrinsicSupportCache.try_emplace(IntrinsicID);
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if (Inserted)
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It->second = checkFeatureExpression(RequiredFeatures);
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return It->second;
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}
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bool TargetSubtargetInfo::enableAtomicExpand() const {
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return true;
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}
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bool TargetSubtargetInfo::enableIndirectBrExpand() const {
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return false;
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}
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bool TargetSubtargetInfo::enableMachineScheduler() const {
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return false;
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}
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bool TargetSubtargetInfo::enableJoinGlobalCopies() const {
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return enableMachineScheduler();
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}
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bool TargetSubtargetInfo::enableRALocalReassignment(
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CodeGenOptLevel OptLevel) const {
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return true;
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}
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bool TargetSubtargetInfo::enablePostRAScheduler() const {
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return getSchedModel().PostRAScheduler;
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}
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bool TargetSubtargetInfo::enablePostRAMachineScheduler() const {
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return enableMachineScheduler() && enablePostRAScheduler();
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}
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bool TargetSubtargetInfo::useAA() const {
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return false;
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}
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void TargetSubtargetInfo::mirFileLoaded(MachineFunction &MF) const { }
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