llvm-tms34010

opencode.siil.arti.ee/llvm-tms34010

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arti 4ff6e2df9d tms34010: select MPYS/MPYU/DIVS/DIVU for 32-bit arithmetic

Add the register-file multiply and divide encodings and restrict their tied
destination to the odd allocatable A registers, so the instruction uses the
single-register 32-bit form instead of a Rd:Rd+1 pair.  MPYS covers the low
32 bits of a 32x32 product, MPYU the masked 16x16 unsigned product, and
DIVS/DIVU the 32/32 quotients.  SREM/UREM expand to dividend - quotient *
divisor because the odd-destination divide does not return a remainder.

Sign-extension in register (which DAGCombine forms from ordinary short
arithmetic) selects SEXT8/SEXT16 and expands to the verified SLL/SRA pair.

2026-11-12 06:04:53 +00:00

benchmarks

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bindings

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cmake

workflows/release-binaries: Improve Windows installer (#220414 )

2026-10-13 09:53:43 +02:00

docs

[RISCV] Ensure Shadow Stack checks correct RA

2026-10-28 19:49:04 +00:00

examples

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include

TMS34010: add 32-bit bit-addressed target and clang pointer semantics

2026-11-11 06:00:56 +00:00

lib

tms34010: select MPYS/MPYU/DIVS/DIVU for 32-bit arithmetic

2026-11-12 06:04:53 +00:00

projects

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resources

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runtimes

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test

tms34010: select MPYS/MPYU/DIVS/DIVU for 32-bit arithmetic

2026-11-12 06:04:53 +00:00

tools

[ld64.lld, llvm-otool] Minimal arm64e.x1 support (#222721 )

2026-09-29 11:47:27 +02:00

unittests

[debuginfod] Abort cached file stream if request fails (#232038 )

2026-10-23 06:50:42 +00:00

utils

Bump version to 23.1.5

2026-10-20 15:06:51 +02:00

.clang-format

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.clang-tidy

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.gitattributes

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.gitignore

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CMakeLists.txt

TMS34010: add 32-bit bit-addressed target and clang pointer semantics

2026-11-11 06:00:56 +00:00

CMakePresets.json

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configure

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CREDITS.TXT

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LICENSE.TXT

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Maintainers.md

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README.txt

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RELEASE_TESTERS.TXT

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README.txt

The LLVM Compiler Infrastructure
================================

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Please see the documentation provided in docs/ for further
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