arti
4ff6e2df9d
Add the register-file multiply and divide encodings and restrict their tied destination to the odd allocatable A registers, so the instruction uses the single-register 32-bit form instead of a Rd:Rd+1 pair. MPYS covers the low 32 bits of a 32x32 product, MPYU the masked 16x16 unsigned product, and DIVS/DIVU the 32/32 quotients. SREM/UREM expand to dividend - quotient * divisor because the odd-destination divide does not return a remainder. Sign-extension in register (which DAGCombine forms from ordinary short arithmetic) selects SEXT8/SEXT16 and expands to the verified SLL/SRA pair.
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