341 lines
15 KiB
Markdown
341 lines
15 KiB
Markdown
# tms-c-compiler
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A modern C toolchain for the DEC VT1200 / TI TMS34010, built as a small fork of
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upstream LLVM.
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**Status: M2.** `llc -march=tms34010` emits GSPA-compatible assembly using the
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TI ABI: integer/pointer arguments are pushed on the program stack, the result is
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returned in `A8`, frames use `A13`/`A14`/`A15`, and functions end in `RETS 2`
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(`RETS 0` without arguments). M2 can call a ROM entry point (`strlen`) and emit
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initialized `.data` and string literals. It is still **assembly-only**: no
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object writer, no `clang -c`, and no native COFF; GSPA/GSPLNK under DOSBox
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produce the COFF. Control flow, floats, structs, varargs and function pointers
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remain M3+.
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- Design: [`docs/superpowers/specs/2026-11-10-tms34010-llvm-design.md`](docs/superpowers/specs/2026-11-10-tms34010-llvm-design.md)
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- M0 plan: [`docs/superpowers/plans/2026-11-10-tms34010-m0-fork-and-bit-address-semantics.md`](docs/superpowers/plans/2026-11-10-tms34010-m0-fork-and-bit-address-semantics.md)
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- M1 plan: [`docs/superpowers/plans/2026-11-11-tms34010-m1-minimal-backend.md`](docs/superpowers/plans/2026-11-11-tms34010-m1-minimal-backend.md)
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- M2 plan: [`docs/superpowers/plans/2026-11-11-tms34010-m2-ti-abi-and-rom-calls.md`](docs/superpowers/plans/2026-11-11-tms34010-m2-ti-abi-and-rom-calls.md)
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- Spike: [`spike/REPORT-23.md`](spike/REPORT-23.md) (current, LLVM 23.1.5);
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[`spike/REPORT.md`](spike/REPORT.md) (historical, 19.1.7)
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## Repositories
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- **Compiler fork:** <https://git.wut.ee/opencode.siil.arti.ee/llvm-tms34010>
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(branch `m2`) — the full buildable LLVM 23.1.5 tree with the TMS34010
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target, clang bit-address changes and the M2 backend. Branch `tms34010` is
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the M1 tip and keeps the original M1 backend and suite.
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- **This project:** <https://git.wut.ee/opencode.siil.arti.ee/tms-c-compiler>
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(branch `m2`) — plans/specs, VT1200 integration tooling, `tms-bitaddr`,
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`tms-clang`, symbols, the M2 harness and the spike. Branch `m1` is the
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reproducible M1 snapshot, including the retired M1 harness.
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The compiler fork is the canonical source for all target code. `patches/llvm`
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here is a **frozen M0 mirror** used by the default upstream+patches build; M2
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does not change it.
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## What M2 provides
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M2 replaces the M1 test convention with the TI ABI and stops at assembly:
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- `llc -march=tms34010 -filetype=asm` for straight-line `i32`/pointer
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functions with calls, frames and locals.
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- A caller saves `A14` (STK) on the system stack, pushes arguments on the
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program stack **in reverse order** (each a 32-bit slot), emits `CALLA`,
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then re-establishes both field sizes (`SETF 16,0,0`, `SETF 32,0,1`).
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- A callee starts with `SETF 16,0,0`/`SETF 32,0,1`, saves the used
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A0–A7/A9–A12 registers and the old FP on the system stack, sets `FP = STK`,
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allocates the frame with `ADDI`, and restores both stacks in the epilogue.
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The first explicit argument is at `FP(-32)`, the second at `FP(-64)`, and
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so on; locals live at positive FP offsets.
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- `void`, `i32` and pointer returns, in `A8`; `RETS 2` when the function has
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explicit arguments, `RETS 0` otherwise.
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- Initialized globals, string/byte-array literals and pointer initializers in
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`.data`; zero-initialized mutable globals stay in `.bss`. The loader copies
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`.data` along with `.text`.
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- ROM import stubs generated from `symbols/vt1200-v22.syms`. M2 consumes
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`strlen` only: `_strlen: jauc 3FB458D0h`. `CALLA _strlen` pushes the return
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PC, the stub jumps to the ROM, and the ROM's `RETS 2` returns directly to
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our caller.
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- Thirty-seven `llvm-lit`/FileCheck tests under
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`llvm/test/CodeGen/TMS34010/m2-*.ll`, including negative tests that pin the
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loud refusals. The ABI/data coverage includes `m2-returned`,
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`m2-returned-call`, `m2-call-noret`, `m2-data-align`, `m2-data-avail`,
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`m2-data-z64` and `m2-data-i1`.
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- End-to-end MAME and dis34 gates, plus a differential check against assembly
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generated once by the 1987 TI compiler (see below).
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## The TI ABI
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| | M1 test convention (branch `m1`) | TI ABI (M2) |
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|---|---|---|
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| Integer/pointer arguments | `A0`–`A3`, four maximum | program stack via `A14` (STK), pushed in reverse |
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| Argument slots | registers | first at `FP(-32)`, second at `FP(-64)`, … |
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| Return value | `A0` | `A8` |
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| Frame | none; leaf functions only | `A13` FP, `A14` STK, `A15` system stack |
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| Locals | none | positive FP offsets |
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| Return instruction | `RETS 0` | `RETS 2` with arguments, `RETS 0` without |
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| Calls, callee-saves, stack args | rejected | required |
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| Field size | harness sets FS1/FS0 before entry | `FS0 = 16` and `FS1 = 32`, set in the prologue and after every call |
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The callee-saved set is `A0`–`A7` and `A9`–`A12`; `A8` is the return register
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and `A13`–`A15` are reserved. After `n` system-stack pushes the saved old STK
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is at `SP + (n+1)*32`, and `RETS N` pops the return PC and advances `SP` by
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`32 + 16N`. `FS0` must be 16 and `FS1` must be 32 at function entry and
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immediately after every `CALLA` (`SETF 16,0,0` then `SETF 32,0,1`), because
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ROM code may change either field size. FS0 drives `short` loads/stores and FS1
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drives 32-bit words.
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## Run the M2 gates
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These are the documented commands; all must pass. The M1 harness and suite are
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on branch `m1` and are **not** M2 gates: they encode the retired M1 register
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convention.
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```sh
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# 1. Build llc, opt, clang and the test tools
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ninja -C build/llvm-clean-build llc opt clang llvm-config FileCheck count not
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# 2. LLVM codegen tests: 37 passed
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build/llvm-clean-build/bin/llvm-lit -v \
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build/llvm-clean-build/test/CodeGen/TMS34010 --filter='m2-'
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# 3. Compile, assemble, link and run in MAME
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scripts/tests/m2/run.sh
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# -> M2 MAME: PASS
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# (check=4 first=20 second=22 caller=42 locals=7 keep=16)
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# 4. Rebuild the COFF and check the GSPA encodings with dis34
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scripts/tests/m2/dis-roundtrip.sh
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# -> M2 dis34 round-trip: PASS
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# 5. Differential TI-compiler ABI check (no DOSBox)
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scripts/tests/m2/diff/check.sh
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# -> M2 diff: PASS
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# 6. GEP scaling/normalization tool tests
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tools/tms-bitaddr/tests/run.sh
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# -> tms-bitaddr: PASS
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```
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`scripts/tests/m2/run.sh` compiles five C inputs with `scripts/tms-clang -O2`,
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runs `llc -march=tms34010 -O0 -filetype=asm` on the normalized IR, generates
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the per-ROM import stubs, concatenates the result with `scripts/m2/entry.asm`,
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assembles/links with GSPA/GSPLNK 2.00 under DOSBox, then loads the COFF in
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MAME. It checks `strlen("0::0") == 4`, two-argument order, a direct call, a
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local frame, and callee-saved preservation. Paths are overridable with
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`TMS_CLANG`, `TMS_OPT`, `TMS_BITADDR`, `TMS_LLC`, `MAME`, `DOSBOX`, `SDK_IMG`,
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`M2_WORK`, `M2_COFF` and `M2_SDK`.
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`dis-roundtrip.sh` runs the same build and disassembles the linked `.text` with
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the VT1200 tree's `dis34`, checking the TI-ABI instructions at their linked bit
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addresses, the old-STK restore offset against the push count, and the copied
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`.data` bytes.
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`scripts/tests/m2/diff/check.sh` is the CI golden check. It compares the ABI
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shape of our assembly with stored output from the 1987 TI compiler for the same
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K&R sources: first argument at `FP(-32)`, second at `FP(-64)`, result in `A8`,
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`RETS 2` for `add2`, a nonzero frame and `RETS 0` for `locals`. It does not
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compare instruction selection byte-for-byte. The stored `ti-add2.s` and
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`ti-locals.s` were generated once with `gspcpp`/`gspcc`/`gspcg` (GSP C Compiler
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2.01) under DOSBox; CI never runs DOSBox, it greps the stored files.
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## `.data`, strings and the loader
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GSPA 2.00 has no ELF sections. M2 emits raw `.data` text, never `.rodata`,
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`.asciz`, `.p2align` or `.section`:
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- `i8` scalar or byte/string array: `.byte` with GSPA hex (`068h`)
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- `i16` scalar: `.word`
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- `i32` scalar: `.long`
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- pointer: `.long _symbol+<bit addend>` (the addend is already in bits)
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- `.even` before a `.data` global whose alignment is at least 16 bits, so the
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label and the following `.word`/`.long` agree.
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A scalar's directive must match its width, otherwise the next global's offset
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is wrong. GSPA's `.even` aligns to a 16-bit boundary only, so an explicit
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`align 4`/`align 8` on a `.data` object is **not** honored in M2: the target's
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standalone object alignment is 2 bytes. Private/local symbol names are
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sanitized to GSPA-safe names (`_HH` for non-alphanumerics). Unsupported
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initializer shapes — including arrays whose element width has no GSPA
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directive (`i1`, `i64`) — fail with
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`M2 .data supports only integer, pointer and byte-array initializers`.
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Zero-initialized mutable globals remain `.bss` and are zeroed by the loader.
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## ROM imports
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ROM entry points are per-ROM-revision bit addresses, kept out of the compiler
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in `symbols/vt1200-v22.syms`. `scripts/m2/gen-rom-imports.sh` turns each entry
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into an absolute-jump stub:
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```asm
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.globl _strlen
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_strlen:
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jauc 3FB458D0h
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```
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`JAUC` is the TMS34010 unconditional absolute jump; GSPA 2.00 rejects bare
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`ja`. M2 uses only `strlen`; later milestones extend and validate the table and
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add the Xlib call sequence. Do not add Xlib dependencies to M2.
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## M2 non-goals
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M2 deliberately rejects or omits:
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- **Branches/control flow:** conditional and unconditional branches, loops,
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and spill/fixup paths that need them. A branch that reaches ISel fails
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loudly; M3 owns control flow.
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- **Floating point:** float/double arguments, returns and arithmetic (M5).
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- **Aggregates:** structs/unions by value, `sret`, `byval`, bitfields (M4/M5).
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- **Varargs:** `...` functions and calls (M5).
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- **Function pointers and indirect calls** (M4).
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- **Tail calls:** ordinary `tail` markers are demoted to ordinary calls;
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`musttail` is not implemented (M2 C does not emit it). Real tail calls are
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M3.
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- **Narrow ABI types:** `i8`/`i16` parameters, `i64`, and narrow returns; M3
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adds the widen/truncate rules. Narrow loads/stores inside a function remain
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supported.
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- **Object output:** no `MCCodeEmitter`, object writer, `llc -filetype=obj`,
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`clang -c` or native COFF. GSPA assembles and GSPLNK links the asm.
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- **Xlib and clients:** no X11 headers, Xlib calls or real VT1200 clients in
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M2; only the `strlen` ROM call.
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The optimizer's `returned` argument attribute is accepted because it does not
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affect the stack-slot ABI; `sret`/`byval`/`inreg`/`nest` remain rejected.
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## Repository layout
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```text
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build/llvm-clean/ compiler fork checkout used for M2 (ignored)
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build/llvm-clean-build/ its Ninja build tree (ignored)
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build/llvm-src/ M0 working fork (ignored)
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patches/llvm/ frozen M0 patch series against llvmorg-23.1.5
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tools/tms-bitaddr/ GEP scale/normalize tool
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scripts/tms-clang IR pipeline wrapper (clang + tms-bitaddr + opt)
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scripts/m2/ M2 harness: C inputs, entry.asm, link.cmd, stubs, checks
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scripts/tests/m2/ M2 gates (run.sh, dis-roundtrip.sh)
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scripts/tests/m2/diff/ TI golden asm and the differential ABI check
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scripts/m1/ M1 harness (historical; also on branch `m1`, not an M2 gate)
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scripts/tests/m1/ M1 gates (historical; also on branch `m1`, not an M2 gate)
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scripts/tests/m0/ M0 integration tests
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scripts/build-llvm.sh fork or upstream+patches build
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scripts/fetch-vt1200.sh fetch the VT1200 RE tree at its pinned commit
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spike/ measurement corpus and reports
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symbols/ per-ROM import tables (v2.2 subset)
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vendor/ fetched assets and LLVM sources (ignored)
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docs/ design and plans
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```
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## Prerequisites
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`cmake`, `ninja-build`, `ccache`, a C++17 host compiler (GCC 14 is used here),
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Python 3, and about 20 GB of disk for the LLVM source and build. The M2 MAME
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and dis34 gates additionally need `dosbox`, `mtools` (`mcopy`), the VT1200 SDK
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image, the `dwt` COFF loader, `dis34`, and a built MAME `vt1200` binary
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(`build/mame-src/vt1200`). The differential golden check needs no
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DOSBox/MAME/SDK; it needs only the built `clang`, `opt`, `llc` and
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`tools/tms-bitaddr/tms-bitaddr`. On Debian:
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```sh
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sudo apt-get install -y cmake ninja-build ccache dosbox mtools
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```
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## Fetch the VT1200 assets
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The compiler contract is checked against the VT1200 tree (TI `hello.s`, the
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Xlib call sequence, `as34`, `dis34`, SDKs, manuals). It is not vendored:
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```sh
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./scripts/fetch-vt1200.sh # -> vendor/vt1200, pinned 17dfd24...
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```
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## Build the compiler
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### Compiler fork (M2, the normal path)
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The fork checkout already exists at `build/llvm-clean` on `m2`. Build it in
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place:
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```sh
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LLVM_SRC=$PWD/build/llvm-clean LLVM_BRANCH=m2 ./scripts/build-llvm.sh
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# binaries: build/llvm-clean-build/bin/{llc,clang,opt,llvm-config,FileCheck}
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# lit driver: build/llvm-clean-build/bin/llvm-lit
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```
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To clone the fork first instead of using an existing checkout:
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```sh
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LLVM_REPO=gitea@git.wut.ee:opencode.siil.arti.ee/llvm-tms34010.git \
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LLVM_BRANCH=m2 ./scripts/build-llvm.sh
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```
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Fork mode **never** checks out, resets, cleans or patches the source tree; it
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only runs CMake and Ninja. Local commits on the branch are safe. Use
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`LLVM_BUILD=...` to keep a separate build directory. It builds `llc`, clang,
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opt, `llvm-config`, FileCheck and the test helpers with X86 (host) and
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TMS34010; a first build takes roughly 20–40 minutes.
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### Upstream + patches (frozen M0 path)
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```sh
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./scripts/build-llvm.sh
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```
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This mode clones `llvmorg-23.1.5`, applies `patches/llvm/*.patch`, and builds
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`build/llvm-clean-build`. It owns and resets only a plain `llvm-project` clone:
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if `build/llvm-clean` has some other origin (for example the M2 fork), it
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refuses rather than destroying it. Use fork mode for that checkout.
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`scripts/export-patches.sh` regenerates the committed M0 patch series with
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`git diff` (including new files via `git add -N`); it is not used for M1/M2.
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## Build the M0 support tools
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The M2 pipeline uses `tms-bitaddr` and `tms-clang`:
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```sh
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LLVM_CONFIG=$PWD/build/llvm-clean-build/bin/llvm-config \
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tools/tms-bitaddr/build.sh
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```
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M0 regression test (optional in M2):
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```sh
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TMS_CLANG=$PWD/build/llvm-clean-build/bin/clang \
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TMS_OPT=$PWD/build/llvm-clean-build/bin/opt \
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TMS_BITADDR=$PWD/tools/tms-bitaddr/tms-bitaddr \
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./scripts/tests/m0/run.sh
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# -> M0 pipeline: PASS
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```
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## Emit assembly by hand
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```sh
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TMS_CLANG=$PWD/build/llvm-clean-build/bin/clang \
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TMS_OPT=$PWD/build/llvm-clean-build/bin/opt \
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TMS_BITADDR=$PWD/tools/tms-bitaddr/tms-bitaddr \
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scripts/tms-clang -O2 -o /tmp/add2.ll scripts/tests/m2/diff/ti-add2.c
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build/llvm-clean-build/bin/llc -march=tms34010 -O0 -filetype=asm \
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/tmp/add2.ll -o /tmp/add2.s
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```
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The resulting function loads its arguments at `FP(-32)` and `FP(-64)`, returns
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in `A8`, and ends in `RETS 2`. Always produce the IR with `scripts/tms-clang`
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(or run `tms-bitaddr --scale`) before `llc`: raw clang IR carries byte GEP
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offsets, but `llc` treats every surviving GEP offset as a *bit* offset, so
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addresses would be 8× too small. Run `llc -O0` on the normalized IR that
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`tms-clang` already optimized and scaled. `tms-bitaddr --normalize` consumes
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that scaled IR and rejects a typed (non-`i8`) or vector GEP instead of emitting
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its byte offset as bits. The lit tests use
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`llc -march=tms34010 -O2 -filetype=asm` on hand-written IR to exercise the
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selector pipeline directly. Output is assembly only: `llc` cannot emit an
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object file or a usable COFF for this target.
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## Later milestones
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M3 adds branches/control flow, the Xlib call sequence and a wider validated ROM
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symbol table. M4 adds the real client plus structs and function pointers. M5
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adds the native COFF path, floats, varargs, bitfields and `long long`; 2ine
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r5.01 is a later speed-up for the GSPA/GSPLNK step.
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