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fw/spi.c: explain why we probably can't reach fosc/2 = 4 MHz

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This commit is contained in:
Werner Almesberger 2012-06-23 14:54:31 -03:00
parent 5b1f722568
commit dd72f4642e
1 changed files with 10 additions and 0 deletions
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10
fw/spi.c
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@ -24,6 +24,16 @@
#define SCLK B, 8
/*
* According to simulation, signals from MCU to transceiver should already
* suffer severe degradation * at fosc/4 = 2 MHz due to parasitic capacitance
* (assumed to be 10 pF) and the series resistors (10 kOhm) of the voltage
* dividers.
*
* fosc/2 = 4 MHz looks horrible in simulation and does not work reliably in
* practice either.
*/
void spi_init(void)
{
/* SPI mode 0, MSB first, fosc/4 */