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regs4740.h: added DMAC registers; added virt to phys translation; cleanup

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- regs4740.h (REG_PADDR): translate a register access to the
  corresponding physical address
- regs4740.h (REG_WINDOW): added register window size
- regs4740.h (CGU, INT, TCU, GPIO, MSC): prefix register group macros
  with an underscore, to avoid name collision with DMAC
- regs4740.h: added DMAC registers
- regs4740.h (MSC_NOP): should be MSC_NOB
This commit is contained in:
Werner Almesberger 2011-04-29 21:49:23 -03:00
parent 6cd21404cd
commit 1a7b5015f1
1 changed files with 51 additions and 35 deletions
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86
ubb-vga/regs4740.h
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@ -17,47 +17,63 @@
#define SOC_BASE 0x10000000 #define SOC_BASE 0x10000000
#define REG_WINDOW 0x4000000
#define REG(n) (*(volatile uint32_t *) ((REG_BASE_PTR)+(n))) #define REG(n) (*(volatile uint32_t *) ((void *) (REG_BASE_PTR)+(n)))
#define CGU(n) REG(0x00000+(n)) #define REG_PADDR(r) ((unsigned long) \
#define INTC(n) REG(0x01000+(n)) ((void *) &(r)-(void *) (REG_BASE_PTR)+SOC_BASE))
#define TCU(n) REG(0x02000+(n))
#define GPIO(n) REG(0x10000+(n))
#define MSC(n) REG(0x21000+(n))
#define CLKGR CGU(0x0020) /* Clock Gate */ #define _CGU(n) REG(0x0000000+(n))
#define MSCCDR CGU(0x0068) /* MSC device clock divider */ #define _INTC(n) REG(0x0001000+(n))
#define _TCU(n) REG(0x0002000+(n))
#define _GPIO(n) REG(0x0010000+(n))
#define _MSC(n) REG(0x0021000+(n))
#define _DMAC(n) REG(0x3020000+(n))
#define PDPIN GPIO(0x300) /* port D pin level */ #define CLKGR _CGU(0x0020) /* Clock Gate */
#define PDDATS GPIO(0x314) /* port D data set */ #define MSCCDR _CGU(0x0068) /* MSC device clock divider */
#define PDDATC GPIO(0x318) /* port D data clear */
#define PDFUNS GPIO(0x344) /* port D function set */
#define PDFUNC GPIO(0x348) /* port D function clear */
#define PDDIRS GPIO(0x364) /* port D direction set */
#define PDDIRC GPIO(0x368) /* port D direction clear */
#define ICMR INTC(0x04) /* Interrupt controller mask */ #define PDPIN _GPIO(0x300) /* port D pin level */
#define ICMSR INTC(0x08) /* Interrupt controller mask set */ #define PDDATS _GPIO(0x314) /* port D data set */
#define ICMCR INTC(0x0c) /* Interrupt controller mask clear */ #define PDDATC _GPIO(0x318) /* port D data clear */
#define PDFUNS _GPIO(0x344) /* port D function set */
#define PDFUNC _GPIO(0x348) /* port D function clear */
#define PDDIRS _GPIO(0x364) /* port D direction set */
#define PDDIRC _GPIO(0x368) /* port D direction clear */
#define TSSR TCU(0x2c) /* Timer STOP set */ #define ICMR _INTC(0x04) /* Interrupt controller mask */
#define TSCR TCU(0x3c) /* Timer STOP clear */ #define ICMSR _INTC(0x08) /* Interrupt controller mask set */
#define TESR TCU(0x14) /* Timer counter enable set */ #define ICMCR _INTC(0x0c) /* Interrupt controller mask clear */
#define TECR TCU(0x18) /* Timer counter enable clear */
#define TCSR(n) TCU(0x4c+0x10*(n)) /* Timer control */
#define TDFR(n) TCU(0x40+0x10*(n)) /* Timer data full */
#define TCNT(n) TCU(0x48+0x10*(n)) /* Timer counter */
#define MSC_STRPCL MSC(0x00) /* Start/stop MMC/SD clock */ #define TSSR _TCU(0x2c) /* Timer STOP set */
#define MSC_STAT MSC(0x04) /* MSC status */ #define TSCR _TCU(0x3c) /* Timer STOP clear */
#define MSC_CLKRT MSC(0x08) /* MSC clock rate */ #define TESR _TCU(0x14) /* Timer counter enable set */
#define MSC_CMDAT MSC(0x0c) /* MMC/SD command and data control */ #define TECR _TCU(0x18) /* Timer counter enable clear */
#define MSC_RESTO MSC(0x10) /* MMC/SD response time out */ #define TCSR(n) _TCU(0x4c+0x10*(n)) /* Timer control */
#define MSC_BLKLEN MSC(0x18) /* MMC/SD block length */ #define TDFR(n) _TCU(0x40+0x10*(n)) /* Timer data full */
#define MSC_NOP MSC(0x1c) /* MMC/SD number of blocks */ #define TCNT(n) _TCU(0x48+0x10*(n)) /* Timer counter */
#define MSC_CMD MSC(0x2c) /* MMC/SD command index */
#define MSC_ARG MSC(0x30) /* MMC/SD command argument */ #define MSC_STRPCL _MSC(0x00) /* Start/stop MMC/SD clock */
#define MSC_TXFIFO MSC(0x3c) /* MMC/SD transmit data FIFO */ #define MSC_STAT _MSC(0x04) /* MSC status */
#define MSC_CLKRT _MSC(0x08) /* MSC clock rate */
#define MSC_CMDAT _MSC(0x0c) /* MMC/SD command and data control */
#define MSC_RESTO _MSC(0x10) /* MMC/SD response time out */
#define MSC_BLKLEN _MSC(0x18) /* MMC/SD block length */
#define MSC_NOB _MSC(0x1c) /* MMC/SD number of blocks */
#define MSC_CMD _MSC(0x2c) /* MMC/SD command index */
#define MSC_ARG _MSC(0x30) /* MMC/SD command argument */
#define MSC_TXFIFO _MSC(0x3c) /* MMC/SD transmit data FIFO */
#define _DMAn(n, r) _DMAC(0x20*(n)+(r))
#define DSA(n) _DMAn(n, 0x00) /* DMA source address */
#define DTA(n) _DMAn(n, 0x04) /* DMA target address */
#define DTC(n) _DMAn(n, 0x08) /* DMA transfer count */
#define DRT(n) _DMAn(n, 0x0c) /* DMA request type */
#define DCS(n) _DMAn(n, 0x10) /* DMA channel control/status */
#define DCM(n) _DMAn(n, 0x14) /* DMA command */
#define DMAC _DMAC(0x300) /* DMA control */
#define DDR _DMAC(0x308) /* DMA doorbell */
#endif /* !REGS4740_H */ #endif /* !REGS4740_H */