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ubb-vga2: instead of pointers to registers, use pointer plus offset (via macros)
- regs4740.h: macros to access selected Jz4740 registers - ubb-vga2.c: replaced all pointers to registers with access macros - ubb-vga2.c (line_cycles): we now seem to be 0.1 us slower
This commit is contained in:
Werner Almesberger
parent
cb5a6bd202
commit
957491d209
63
ubb-vga/regs4740.h
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63
ubb-vga/regs4740.h
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@ -0,0 +1,63 @@
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/*
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* regs4740.h - Jz4740 register definitions (subset)
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*
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* Written 2011 by Werner Almesberger
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* Copyright 2011 Werner Almesberger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef REGS4740_H
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#define REGS4740_H
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#include <stdint.h>
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#define SOC_BASE 0x10000000
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#define REG(n) (*(volatile uint32_t *) ((REG_BASE_PTR)+(n)))
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#define CGU(n) REG(0x00000+(n))
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#define INTC(n) REG(0x01000+(n))
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#define TCU(n) REG(0x02000+(n))
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#define GPIO(n) REG(0x10000+(n))
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#define MSC(n) REG(0x21000+(n))
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#define CLKGR CGU(0x0020) /* Clock Gate */
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#define MSCCDR CGU(0x0068) /* MSC device clock divider */
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#define PDPIN GPIO(0x300) /* port D pin level */
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#define PDDATS GPIO(0x314) /* port D data set */
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#define PDDATC GPIO(0x318) /* port D data clear */
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#define PDFUNS GPIO(0x344) /* port D function set */
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#define PDFUNC GPIO(0x348) /* port D function clear */
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#define PDDIRS GPIO(0x364) /* port D direction set */
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#define PDDIRC GPIO(0x368) /* port D direction clear */
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#define ICMR INTC(0x04) /* Interrupt controller mask */
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#define ICMSR INTC(0x08) /* Interrupt controller mask set */
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#define ICMCR INTC(0x0c) /* Interrupt controller mask clear */
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#define TSSR TCU(0x2c) /* Timer STOP set */
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#define TSCR TCU(0x3c) /* Timer STOP clear */
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#define TESR TCU(0x14) /* Timer counter enable set */
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#define TECR TCU(0x18) /* Timer counter enable clear */
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#define TCSR(n) TCU(0x4c+0x10*(n)) /* Timer control */
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#define TDFR(n) TCU(0x40+0x10*(n)) /* Timer data full */
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#define TCNT(n) TCU(0x48+0x10*(n)) /* Timer counter */
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#define MSC_STRPCL MSC(0x00) /* Start/stop MMC/SD clock */
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#define MSC_STAT MSC(0x04) /* MSC status */
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#define MSC_CLKRT MSC(0x08) /* MSC clock rate */
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#define MSC_CMDAT MSC(0x0c) /* MMC/SD command and data control */
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#define MSC_RESTO MSC(0x10) /* MMC/SD response time out */
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#define MSC_BLKLEN MSC(0x18) /* MMC/SD block length */
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#define MSC_NOP MSC(0x1c) /* MMC/SD number of blocks */
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#define MSC_CMD MSC(0x2c) /* MMC/SD command index */
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#define MSC_ARG MSC(0x30) /* MMC/SD command argument */
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#define MSC_TXFIFO MSC(0x3c) /* MMC/SD transmit data FIFO */
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#endif /* !REGS4740_H */
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@ -34,6 +34,7 @@
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#include <fcntl.h>
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#include <sys/mman.h>
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#include "regs4740.h"
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#include "ubb-vga.h"
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@ -41,6 +42,10 @@
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#define YRES 480
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#define REG_BASE_PTR base
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static volatile void *base;
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static int bad;
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@ -69,27 +74,11 @@ static int bad;
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#define PAGE_SIZE 4096
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#define SOC_BASE 0x10000000
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static volatile uint32_t *icmr, *icmsr, *icmcr;
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static uint32_t old_icmr;
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static volatile uint32_t *clkgr, *msccdr;
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static uint32_t old_clkgr;
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static volatile uint32_t *pddats, *pddatc;
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static volatile uint32_t *pddirs, *pddirc;
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static volatile uint32_t *pdfuns, *pdfunc;
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static volatile uint32_t *tssr, *tscr;
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static volatile uint32_t *tesr, *tecr;
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static volatile uint32_t *tcsr, *tdfr, *tcnt;
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static volatile uint32_t *msc_strpcl, *msc_stat, *msc_clkrt;
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static volatile uint32_t *msc_cmdat, *msc_resto, *msc_blklen, *msc_nob;
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static volatile uint32_t *msc_cmd, *msc_arg, *msc_txfifo;
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static void disable_interrupts(void)
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{
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@ -100,14 +89,14 @@ static void disable_interrupts(void)
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* incorrect mask when restoring interrupts, which may hang the system.
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*/
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old_icmr = *icmr;
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*icmsr = 0xffffffff;
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old_icmr = ICMR;
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ICMSR = 0xffffffff;
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}
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static void enable_interrupts(void)
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{
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*icmcr = ~old_icmr;
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ICMCR = ~old_icmr;
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}
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@ -118,30 +107,30 @@ static void enable_interrupts(void)
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static void disable_lcd(void)
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{
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old_clkgr = *clkgr;
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*clkgr = old_clkgr | 1 << 10;
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old_clkgr = CLKGR;
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CLKGR = old_clkgr | 1 << 10;
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}
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static void enable_lcd(void)
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{
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*clkgr = old_clkgr;
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CLKGR = old_clkgr;
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}
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static void get_timer(void)
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{
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*tscr = 1 << TIMER; /* enable clock */
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*tcsr = 1; /* count at PCLK/1 */
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*tdfr = 0xffff; /* count to 0xffff */
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*tesr = 1 << TIMER;
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TSCR = 1 << TIMER; /* enable clock */
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TCSR(TIMER) = 1; /* count at PCLK/1 */
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TDFR(TIMER) = 0xffff; /* count to 0xffff */
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TESR = 1 << TIMER;
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}
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static void release_timer(void)
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{
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*tecr = 1 << TIMER;
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*tssr = 1 << TIMER;
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TECR = 1 << TIMER;
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TSSR = 1 << TIMER;
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}
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@ -167,43 +156,8 @@ void *map(off_t addr, size_t size)
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static void ben_setup(void)
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{
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volatile void *base;
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base = map(SOC_BASE, PAGE_SIZE*3*16);
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clkgr = base+0x20;
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msccdr = base+0x68;
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icmr = base+0x1004;
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icmsr = base+0x1008;
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icmcr = base+0x100c;
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pddats = base+0x10314;
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pddatc = base+0x10318;
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pdfuns = base+0x10344;
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pdfunc = base+0x10348;
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pddirs = base+0x10364;
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pddirc = base+0x10368;
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tssr = base+0x202c;
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tscr = base+0x203c;
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tesr = base+0x2014;
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tecr = base+0x2018;
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tcsr = base+0x204c+0x10*TIMER;
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tdfr = base+0x2040+0x10*TIMER;
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tcnt = base+0x2048+0x10*TIMER;
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msc_strpcl = base+0x21000;
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msc_stat = base+0x21004;
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msc_clkrt = base+0x21008;
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msc_cmdat = base+0x2100c;
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msc_resto = base+0x21010;
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msc_blklen = base+0x21018;
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msc_nob = base+0x2101c;
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msc_cmd = base+0x2102c;
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msc_arg = base+0x21030;
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msc_txfifo = base+0x2103c;
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/*
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* Ironically, switching the LCD clock on and off many times only
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* increases the risk of a hang. Therefore, we leave stop it during
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@ -229,7 +183,7 @@ static void cleanup(void)
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static void until(uint16_t cycles)
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{
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while ((*tcnt & 0xffff) < cycles);
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while ((TCNT(TIMER) & 0xffff) < cycles);
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}
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@ -239,9 +193,9 @@ static void until(uint16_t cycles)
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static int line_words = XRES/8;
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//static int line_cycles = US(36); /* nominally 31.77 us, but we're too slow */
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//static int line_cycles = US(32); /* nominally 31.77 us, but we're too slow */
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static int line_cycles = US(29.6); /* nominally 31.77 us, but we're too fast */
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static int line_cycles = US(29.7); /* nominally 31.77 us, but we're too fast */
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/*
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* Note: 29.5 is already too short. Tricky timing.
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* Note: 29.6 is already too short. Tricky timing.
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*/
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void setup(void)
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@ -249,16 +203,16 @@ void setup(void)
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mlockall(MCL_CURRENT | MCL_FUTURE);
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ben_setup();
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*pdfuns = R | G | B | Y;
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*pdfunc = VSYNC | HSYNC;
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*pddirs = VSYNC | HSYNC | R | G | B | Y;
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*pddats = VSYNC | HSYNC;
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*pddatc = R | G | B | Y;
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PDFUNS = R | G | B | Y;
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PDFUNC = VSYNC | HSYNC;
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PDDIRS = VSYNC | HSYNC | R | G | B | Y;
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PDDATS = VSYNC | HSYNC;
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PDDATC = R | G | B | Y;
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// *msccdr = 20; /* set the MSC clock to 336 MHz / 21 = 16 MHz */
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*msccdr = 11; /* set the MSC clock to 336 MHz / 12 = 28 MHz */
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*clkgr &= ~(1 << 7); /* enable MSC clock */
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*msc_clkrt = 0; /* bus clock = MSC clock / 1 */
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MSCCDR = 11; /* set the MSC clock to 336 MHz / 12 = 28 MHz */
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CLKGR &= ~(1 << 7); /* enable MSC clock */
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MSC_CLKRT = 0; /* bus clock = MSC clock / 1 */
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}
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@ -269,10 +223,10 @@ static void line(const uint32_t *line)
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/* Back porch */
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*tcnt = 0;
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TCNT(TIMER) = 0;
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*msc_strpcl = 1 << 3; /* reset the MSC */
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// while (*msc_stat & (1 << 15));
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MSC_STRPCL = 1 << 3; /* reset the MSC */
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// while (MSC_STAT & (1 << 15));
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first = *p++;
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@ -280,16 +234,16 @@ static void line(const uint32_t *line)
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/* HSYNC */
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*pddatc = HSYNC;
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*msc_strpcl = 2; /* start MMC clock output */
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PDDATC = HSYNC;
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MSC_STRPCL = 2; /* start MMC clock output */
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*msc_cmdat =
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MSC_CMDAT =
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(1 << 10) | /* 4 bit bus */
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(1 << 4) | /* write */
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(1 << 3) | /* with data transfer */
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1; /* R1 response */
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*msc_strpcl = 4; /* START_OP */
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MSC_STRPCL = 4; /* START_OP */
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until(US(0.79+3.77-0.3));
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/*
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@ -317,11 +271,11 @@ static void line(const uint32_t *line)
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/* Front porch */
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*msc_txfifo = first;
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MSC_TXFIFO = first;
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*pdfuns = CMD;
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*pddats = HSYNC;
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*pdfunc = CMD;
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PDFUNS = CMD;
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PDDATS = HSYNC;
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PDFUNC = CMD;
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/*
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* We don't wait for the end of the front porch because the beginning
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@ -330,20 +284,20 @@ static void line(const uint32_t *line)
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*/
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#if 0 /* quick load */
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*msc_txfifo = *p++;
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*msc_txfifo = *p++;
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MSC_TXFIFO = *p++;
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MSC_TXFIFO = *p++;
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#endif
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while (p != line+line_words) {
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uint8_t st;
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do {
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st = *msc_stat;
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st = MSC_STAT;
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if (st & 3) {
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bad++;
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goto fail;
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}
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}
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while (st & (1 << 7));
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*msc_txfifo = *p++;
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MSC_TXFIFO = *p++;
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}
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fail:
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@ -354,10 +308,10 @@ fail:
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static void hdelay(int cycles)
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{
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while (cycles--) {
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*tcnt = 0;
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*pddatc = HSYNC;
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TCNT(TIMER) = 0;
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PDDATC = HSYNC;
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until(US(3.77));
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*pddats = HSYNC;
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PDDATS = HSYNC;
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until(line_cycles);
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}
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}
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@ -368,9 +322,9 @@ static void frame(const uint32_t *f)
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const uint32_t *p;
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/* VSYNC */
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*pddatc = VSYNC;
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PDDATC = VSYNC;
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hdelay(2);
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*pddats = VSYNC;
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PDDATS = VSYNC;
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/* Front porch */
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@ -380,10 +334,10 @@ static void frame(const uint32_t *f)
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* The horizontal back porch of the previous line is handled inside
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* "line", so we have to wait for less than a full line here.
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*/
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*tcnt = 0;
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*pddatc = HSYNC;
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TCNT(TIMER) = 0;
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PDDATC = HSYNC;
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until(US(3.77));
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*pddats = HSYNC;
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PDDATS = HSYNC;
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until(line_cycles-US(0.79));
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for (p = f; p != f+YRES*line_words; p += line_words)
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