ubb-vga2: instead of pointers to registers, use pointer plus offset (via macros)

- regs4740.h: macros to access selected Jz4740 registers
- ubb-vga2.c: replaced all pointers to registers with access macros
- ubb-vga2.c (line_cycles): we now seem to be 0.1 us slower

ubb-vga/regs4740.h

@@ -0,0 +1,63 @@
+/*
+ * regs4740.h - Jz4740 register definitions (subset)
+ *
+ * Written 2011 by Werner Almesberger
+ * Copyright 2011 Werner Almesberger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef REGS4740_H
+#define	REGS4740_H
+
+#include <stdint.h>
+
+
+#define	SOC_BASE	0x10000000
+
+#define	REG(n)	(*(volatile uint32_t *) ((REG_BASE_PTR)+(n)))
+
+#define	CGU(n)	REG(0x00000+(n))
+#define	INTC(n)	REG(0x01000+(n))
+#define	TCU(n)	REG(0x02000+(n))
+#define	GPIO(n)	REG(0x10000+(n))
+#define	MSC(n)	REG(0x21000+(n))
+
+#define	CLKGR	CGU(0x0020)	/* Clock Gate */
+#define	MSCCDR	CGU(0x0068)	/* MSC device clock divider */
+
+#define	PDPIN	GPIO(0x300)	/* port D pin level */
+#define	PDDATS	GPIO(0x314)	/* port D data set */
+#define	PDDATC	GPIO(0x318)	/* port D data clear */
+#define	PDFUNS	GPIO(0x344)	/* port D function set */
+#define	PDFUNC	GPIO(0x348)	/* port D function clear */
+#define	PDDIRS	GPIO(0x364)	/* port D direction set */
+#define	PDDIRC	GPIO(0x368)	/* port D direction clear */
+
+#define	ICMR	INTC(0x04)	/* Interrupt controller mask */
+#define	ICMSR	INTC(0x08)	/* Interrupt controller mask set */
+#define	ICMCR	INTC(0x0c)	/* Interrupt controller mask clear */
+
+#define	TSSR	TCU(0x2c)		/* Timer STOP set */
+#define	TSCR	TCU(0x3c)		/* Timer STOP clear */
+#define	TESR	TCU(0x14)		/* Timer counter enable set */
+#define	TECR	TCU(0x18)		/* Timer counter enable clear */
+#define	TCSR(n)	TCU(0x4c+0x10*(n))	/* Timer control */
+#define	TDFR(n)	TCU(0x40+0x10*(n))	/* Timer data full */
+#define	TCNT(n)	TCU(0x48+0x10*(n))	/* Timer counter */
+
+#define	MSC_STRPCL	MSC(0x00)	/* Start/stop MMC/SD clock */
+#define	MSC_STAT	MSC(0x04)	/* MSC status */
+#define	MSC_CLKRT	MSC(0x08)	/* MSC clock rate */
+#define	MSC_CMDAT	MSC(0x0c)	/* MMC/SD command and data control */
+#define	MSC_RESTO	MSC(0x10)	/* MMC/SD response time out */
+#define	MSC_BLKLEN	MSC(0x18)	/* MMC/SD block length */
+#define	MSC_NOP		MSC(0x1c)	/* MMC/SD number of blocks */
+#define	MSC_CMD		MSC(0x2c)	/* MMC/SD command index */
+#define	MSC_ARG		MSC(0x30)	/* MMC/SD command argument */
+#define	MSC_TXFIFO	MSC(0x3c)	/* MMC/SD transmit data FIFO */
+
+#endif /* !REGS4740_H */