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ubb-patgen/: flush dcache and write buffer before doing DMA
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@ -11,7 +11,7 @@
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#
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CC = mipsel-openwrt-linux-gcc
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CFLAGS = -g -Wall -O9 -I../libubb/include
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CFLAGS = -g -Wall -O9 -march=mips32 -I../libubb/include
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LDFLAGS =
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LDLIBS = -L../libubb -lubb -lm
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@ -18,6 +18,7 @@
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#include <math.h>
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#include <time.h>
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#include <assert.h>
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#include <asm/cachectl.h>
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#include <ubb/ubb.h>
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#include <ubb/regs4740.h>
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@ -25,9 +26,13 @@
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#include <ubb/physmem.h>
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#define USE_DMA
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#define DMA 5
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extern int cacheflush(char *addr, int nbytes, int cache);
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/* ----- List available bus clock frequencies ------------------------------ */
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@ -309,6 +314,13 @@ static void send_buffer(const struct mmcclk *clk,
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#ifdef USE_DMA
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unsigned long phys;
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if (cacheflush((void *) buf, nibbles >> 1, DCACHE)) {
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perror("cacheflush");
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exit(1);
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}
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asm("sync"); /* flush the write buffer */
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phys = physmem_xlat((void *) buf);
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mmc_buffer(clk, buf[0] >> 4, phys, nibbles, mask);
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#else
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