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mirror of git://projects.qi-hardware.com/ben-blinkenlights.git synced 2024-11-23 18:04:05 +02:00

Added simple UART 8:10 card.

- BOOKSHELF: ATmega48 data sheet
- Makefile (dsv): added target to populate the book shelf
- components/atmega48-mmu.lib, components/atmega48-mmu.dcm: ATmega48-MMU
  schematics symbol
- usrt.pro, uart.sch, uart.cmp, uart.brd: ATmega48-based UART board
This commit is contained in:
Werner Almesberger 2011-01-31 19:02:50 -03:00
parent 623c32304e
commit e7ec5c8ad4
8 changed files with 1883 additions and 2 deletions

13
BOOKSHELF Normal file
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@ -0,0 +1,13 @@
#
# Tags:
#
# N name to use for dsv (must be first)
# A alias name(s)
# D data sheet url
#
N: atmega48
A: atmega88
A: atmega168
A: avr
D: http://www.atmel.com/dyn/resources/prod_documents/doc2545.pdf

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@ -1,7 +1,7 @@
.PHONY: all gen generate sch brd .PHONY: all gen generate sch brd dsv
all: all:
@echo "make what ? target: gen sch brd xpdf" @echo "make what ? target: dsv gen sch brd"
@exit 1 @exit 1
gen generate: gen generate:
@ -13,3 +13,6 @@ sch:
brd: brd:
pcbnew `pwd`/bbl.brd pcbnew `pwd`/bbl.brd
dsv:
../eda-tools/dsv/dsv setup BOOKSHELF

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@ -0,0 +1,3 @@
EESchema-DOCLIB Version 2.0 Date: Mon Jan 31 15:41:03 2011
#
#End Doc Library

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@ -0,0 +1,46 @@
EESchema-LIBRARY Version 2.3 Date: Mon Jan 31 15:41:03 2011
#
# ATmega48-MMU
#
DEF ATmega48-MMU U 0 40 Y Y 1 F N
F0 "U" -1350 1200 60 H V C CNN
F1 "ATmega48-MMU" 0 0 60 H V C CNN
DRAW
T 0 -1350 350 50 0 0 0 INT1 Normal 0 L B
T 0 -1350 -550 50 0 0 0 T1 Normal 0 L B
T 0 -1350 -250 50 0 0 0 TOSC1 Normal 0 L B
T 0 -1350 -400 50 0 0 0 TOSC2 Normal 0 L B
S -1400 1100 1400 -1100 0 0 0 N
X PD3/PCINT9/OC2B/ 1 -1700 450 300 R 50 50 1 1 T
X PD4/PCINT20/XCK/T0 2 -1700 300 300 R 50 50 1 1 T
X VCC 3 -1700 150 300 R 50 50 1 1 W
X GND 4 -1700 0 300 R 50 50 1 1 W
X PB6/PCINT6/XTAL1/ 5 -1700 -150 300 R 50 50 1 1 T
X PB7/PCINT7/XTAL2/ 6 -1700 -300 300 R 50 50 1 1 T
X PD5/PCINT21/OC0B/ 7 -1700 -450 300 R 50 50 1 1 T
X PD6/PCINT22/OC0A/AIN0 8 -450 -1400 300 U 50 50 1 1 T
X PD7/PCINT23/AIN1 9 -300 -1400 300 U 50 50 1 1 T
X PB9/PCINT0/CLKO/ICP1 10 -150 -1400 300 U 50 50 1 1 T
X PC1/ADC1/PCINT9 20 1700 300 300 L 50 50 1 1 T
X PB1/PCINT1/OC1A 11 0 -1400 300 U 50 50 1 1 T
X PC2/ADC2/PCINT10 21 1700 450 300 L 50 50 1 1 T
X PB2/PCINT2/OC1B 12 150 -1400 300 U 50 50 1 1 T
X PC3/ADC3/PCINT11 22 450 1400 300 D 50 50 1 1 T
X PB3/PCINT3/OC2A/MOSI 13 300 -1400 300 U 50 50 1 1 T
X PC4/ADC4/SDA/PCINT12 23 300 1400 300 D 50 50 1 1 T
X PB4/PCINT4/MISO 14 450 -1400 300 U 50 50 1 1 T
X PC5/ADC5/SCL/PCINT13 24 150 1400 300 D 50 50 1 1 T
X PB5/SCK/PCINT5 15 1700 -450 300 L 50 50 1 1 T
X PC6/RESET/PCINT14 25 0 1400 300 D 50 50 1 1 T
X AVCC 16 1700 -300 300 L 50 50 1 1 W
X PD0/RXD/PCINT16 26 -150 1400 300 D 50 50 1 1 T
X AREF 17 1700 -150 300 L 50 50 1 1 W
X PD1/TXD/PCINT17 27 -300 1400 300 D 50 50 1 1 T
X GND 18 1700 0 300 L 50 50 1 1 W
X PD2/INT0/PCINT18 28 -450 1400 300 D 50 50 1 1 T
X PC0/ADC0/PCINT8 19 1700 150 300 L 50 50 1 1 T
X PAD 29 900 -1400 300 U 50 50 1 1 W
ENDDRAW
ENDDEF
#
#End Library

1326
uart/uart.brd Normal file

File diff suppressed because it is too large Load Diff

80
uart/uart.cmp Normal file
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Cmp-Mod V01 Created by CvPCB (2010-12-27 BZR 2685)-unstable date = Mon Jan 31 18:30:06 2011
BeginCmp
TimeStamp = /4D470731;
Reference = C1;
ValeurCmp = 100nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4D47260E;
Reference = D1;
ValeurCmp = LED;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4D4704D9;
Reference = K1;
ValeurCmp = CONN_3;
IdModule = PIN_ARRAY_3X1;
EndCmp
BeginCmp
TimeStamp = /4D4702F7;
Reference = P1;
ValeurCmp = 8:10-CARD;
IdModule = 8:10-card;
EndCmp
BeginCmp
TimeStamp = /4D472714;
Reference = P2;
ValeurCmp = CONN_1;
IdModule = PAD_2mm;
EndCmp
BeginCmp
TimeStamp = /4D472716;
Reference = P3;
ValeurCmp = CONN_1;
IdModule = PAD_2mm;
EndCmp
BeginCmp
TimeStamp = /4D47292F;
Reference = P4;
ValeurCmp = CONN_1;
IdModule = PAD_2mm;
EndCmp
BeginCmp
TimeStamp = /4D47052C;
Reference = R1;
ValeurCmp = 100;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4D47052E;
Reference = R2;
ValeurCmp = 100;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4D472610;
Reference = R3;
ValeurCmp = 68;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4D4702FE;
Reference = U1;
ValeurCmp = ATMEGA48-MMU;
IdModule = QFN28-Atmel;
EndCmp
EndListe

71
uart/uart.pro Normal file
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update=Mon Jan 31 19:00:31 2011
last_client=pcbnew
[eeschema]
version=1
LibDir=
NetFmt=1
HPGLSpd=20
HPGLDm=15
HPGLNum=1
offX_A4=0
offY_A4=0
offX_A3=0
offY_A3=0
offX_A2=0
offY_A2=0
offX_A1=0
offY_A1=0
offX_A0=0
offY_A0=0
offX_A=0
offY_A=0
offX_B=0
offY_B=0
offX_C=0
offY_C=0
offX_D=0
offY_D=0
offX_E=0
offY_E=0
RptD_X=0
RptD_Y=100
RptLab=1
LabSize=60
PrintMonochrome=1
ShowSheetReferenceAndTitleBlock=1
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=conn
LibName4=../../kicad-libs/components/8_10-card
LibName5=../components/atmega48-mmu
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[pcbnew]
version=1
PadDrlX=400
PadDimH=800
PadDimV=800
BoardThickness=630
SgPcb45=1
TxtPcbV=800
TxtPcbH=600
TxtModV=600
TxtModH=600
TxtModW=120
VEgarde=100
DrawLar=50
EdgeLar=50
TxtLar=120
MSegLar=150
LastNetListRead=uart.net
[pcbnew/libraries]
LibDir=
LibName1=pin_array
LibName2=../../kicad-libs/modules/stdpass
LibName3=../../kicad-libs/modules/8_10-card
LibName4=../../ben-wpan/modules/qfn
LibName5=../../kicad-libs/modules/pads

339
uart/uart.sch Normal file
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EESchema Schematic File Version 2 date Mon Jan 31 18:30:09 2011
LIBS:power
LIBS:device
LIBS:conn
LIBS:8_10-card
LIBS:atmega48-mmu
LIBS:uart-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 1 1
Title "External UART (3.3 V) as 8:10 card"
Date "31 jan 2011"
Rev "20110131"
Comp "Werner Almesberger"
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Wire Wire Line
3100 3600 2700 3600
Wire Wire Line
2700 3600 2700 4550
Wire Wire Line
2700 4550 2400 4550
Wire Wire Line
2400 4750 4350 4750
Wire Wire Line
4350 4750 4350 4550
Wire Wire Line
3450 1550 3650 1550
Wire Wire Line
8050 5350 5100 5350
Wire Wire Line
5250 4550 5250 5850
Wire Wire Line
5250 5850 8050 5850
Wire Wire Line
8050 5150 6200 5150
Wire Wire Line
1850 3600 1850 4000
Wire Wire Line
3100 3000 1850 3000
Wire Wire Line
6700 3450 6500 3450
Wire Wire Line
3100 3300 2900 3300
Wire Wire Line
2900 3300 2900 5550
Wire Wire Line
2900 5550 8050 5550
Wire Wire Line
4300 1050 4500 1050
Wire Wire Line
3300 1050 3800 1050
Wire Wire Line
3500 1250 3500 950
Wire Wire Line
3500 950 3300 950
Wire Wire Line
4500 1050 4500 1750
Wire Wire Line
4650 1750 4650 850
Wire Wire Line
3300 850 3800 850
Wire Wire Line
4650 850 4300 850
Wire Wire Line
5700 4550 5700 4750
Wire Wire Line
6500 3600 6700 3600
Wire Wire Line
7250 6050 7250 5650
Wire Wire Line
7250 5650 8050 5650
Wire Wire Line
6500 3150 6700 3150
Wire Wire Line
8050 5450 7250 5450
Wire Wire Line
7250 5450 7250 4950
Wire Wire Line
1850 3200 1850 2800
Connection ~ 1850 3000
Wire Wire Line
1850 3800 2350 3800
Connection ~ 1850 3800
Wire Wire Line
2350 3800 2350 3150
Wire Wire Line
2350 3150 3100 3150
Wire Wire Line
4800 1750 4800 850
Wire Wire Line
4800 850 5350 850
Wire Wire Line
8050 5750 6700 5750
Wire Wire Line
6700 5750 6700 3600
Wire Wire Line
5100 5350 5100 4550
Wire Wire Line
8050 5250 7050 5250
Wire Wire Line
7050 5250 7050 2700
Wire Wire Line
7050 2700 6500 2700
Wire Wire Line
2850 1750 2850 1550
Wire Wire Line
2850 1550 3050 1550
Wire Wire Line
4350 1750 4350 1550
Wire Wire Line
4350 1550 4150 1550
Wire Wire Line
2400 4950 4500 4950
Wire Wire Line
4500 4950 4500 4550
$Comp
L CONN_1 P4
U 1 1 4D47292F
P 2250 4950
F 0 "P4" H 2330 4950 40 0000 L CNN
F 1 "CONN_1" H 2250 5005 30 0001 C CNN
F 2 "PAD_2mm" H 2250 4950 60 0001 C CNN
1 2250 4950
-1 0 0 1
$EndComp
$Comp
L GND #PWR01
U 1 1 4D4728FC
P 2850 1750
F 0 "#PWR01" H 2850 1750 30 0001 C CNN
F 1 "GND" H 2850 1680 30 0001 C CNN
1 2850 1750
1 0 0 -1
$EndComp
$Comp
L CONN_1 P3
U 1 1 4D472716
P 2250 4750
F 0 "P3" H 2330 4750 40 0000 L CNN
F 1 "CONN_1" H 2250 4805 30 0001 C CNN
F 2 "PAD_2mm" H 2250 4750 60 0001 C CNN
1 2250 4750
-1 0 0 1
$EndComp
$Comp
L CONN_1 P2
U 1 1 4D472714
P 2250 4550
F 0 "P2" H 2330 4550 40 0000 L CNN
F 1 "CONN_1" H 2250 4605 30 0001 C CNN
F 2 "PAD_2mm" H 2250 4550 60 0001 C CNN
1 2250 4550
-1 0 0 1
$EndComp
$Comp
L R R3
U 1 1 4D472610
P 3900 1550
F 0 "R3" V 3980 1550 50 0000 C CNN
F 1 "68" V 3900 1550 50 0000 C CNN
F 2 "0402" H 3900 1550 60 0001 C CNN
1 3900 1550
0 -1 -1 0
$EndComp
$Comp
L LED D1
U 1 1 4D47260E
P 3250 1550
F 0 "D1" H 3250 1650 50 0000 C CNN
F 1 "LED" H 3250 1450 50 0000 C CNN
F 2 "0603" H 3250 1550 60 0001 C CNN
1 3250 1550
-1 0 0 -1
$EndComp
Text Label 7550 5250 0 60 ~ 0
INT
Text Label 7550 5550 0 60 ~ 0
CLK
Text Label 7550 5150 0 60 ~ 0
nRESET
Text Label 7550 5750 0 60 ~ 0
SCK
Text Label 7550 5850 0 60 ~ 0
MISO
Text Label 7550 5350 0 60 ~ 0
MOSI
Text Label 5000 850 0 60 ~ 0
nRESET
Text Label 6500 5150 2 60 ~ 0
nRESET
$Comp
L C C1
U 1 1 4D470731
P 1850 3400
F 0 "C1" H 1900 3500 50 0000 L CNN
F 1 "100nF" H 1900 3300 50 0000 L CNN
F 2 "0402" H 1850 3400 60 0001 C CNN
1 1850 3400
1 0 0 -1
$EndComp
NoConn ~ 3100 3450
NoConn ~ 6500 2850
NoConn ~ 6500 3000
NoConn ~ 6500 3300
$Comp
L GND #PWR02
U 1 1 4D470651
P 6700 3150
F 0 "#PWR02" H 6700 3150 30 0001 C CNN
F 1 "GND" H 6700 3080 30 0001 C CNN
1 6700 3150
0 -1 -1 0
$EndComp
$Comp
L VDD #PWR03
U 1 1 4D470644
P 1850 2800
F 0 "#PWR03" H 1850 2900 30 0001 C CNN
F 1 "VDD" H 1850 2910 30 0000 C CNN
1 1850 2800
1 0 0 -1
$EndComp
$Comp
L VDD #PWR04
U 1 1 4D470639
P 6700 3450
F 0 "#PWR04" H 6700 3550 30 0001 C CNN
F 1 "VDD" H 6700 3560 30 0000 C CNN
1 6700 3450
0 1 1 0
$EndComp
$Comp
L VDD #PWR05
U 1 1 4D47062B
P 7250 4950
F 0 "#PWR05" H 7250 5050 30 0001 C CNN
F 1 "VDD" H 7250 5060 30 0000 C CNN
1 7250 4950
1 0 0 -1
$EndComp
$Comp
L GND #PWR06
U 1 1 4D470615
P 7250 6050
F 0 "#PWR06" H 7250 6050 30 0001 C CNN
F 1 "GND" H 7250 5980 30 0001 C CNN
1 7250 6050
1 0 0 -1
$EndComp
NoConn ~ 4950 4550
NoConn ~ 4800 4550
NoConn ~ 4650 4550
NoConn ~ 3100 2850
NoConn ~ 3100 2700
NoConn ~ 5250 1750
NoConn ~ 5100 1750
NoConn ~ 4950 1750
$Comp
L R R2
U 1 1 4D47052E
P 4050 1050
F 0 "R2" V 4130 1050 50 0000 C CNN
F 1 "100" V 4050 1050 50 0000 C CNN
F 2 "0402" H 4050 1050 60 0001 C CNN
1 4050 1050
0 -1 -1 0
$EndComp
$Comp
L R R1
U 1 1 4D47052C
P 4050 850
F 0 "R1" V 4130 850 50 0000 C CNN
F 1 "100" V 4050 850 50 0000 C CNN
F 2 "0402" H 4050 850 60 0001 C CNN
1 4050 850
0 -1 -1 0
$EndComp
$Comp
L GND #PWR07
U 1 1 4D4704FA
P 3500 1250
F 0 "#PWR07" H 3500 1250 30 0001 C CNN
F 1 "GND" H 3500 1180 30 0001 C CNN
1 3500 1250
1 0 0 -1
$EndComp
$Comp
L CONN_3 K1
U 1 1 4D4704D9
P 2950 950
F 0 "K1" V 2900 950 50 0000 C CNN
F 1 "CONN_3" V 3000 950 40 0000 C CNN
1 2950 950
-1 0 0 1
$EndComp
$Comp
L GND #PWR08
U 1 1 4D4704BC
P 1850 4000
F 0 "#PWR08" H 1850 4000 30 0001 C CNN
F 1 "GND" H 1850 3930 30 0001 C CNN
1 1850 4000
1 0 0 -1
$EndComp
$Comp
L GND #PWR09
U 1 1 4D4704B4
P 5700 4750
F 0 "#PWR09" H 5700 4750 30 0001 C CNN
F 1 "GND" H 5700 4680 30 0001 C CNN
1 5700 4750
1 0 0 -1
$EndComp
$Comp
L ATMEGA48-MMU U1
U 1 1 4D4702FE
P 4800 3150
F 0 "U1" H 3450 4350 60 0000 C CNN
F 1 "ATMEGA48-MMU" H 4800 3150 60 0000 C CNN
F 2 "QFN28-Atmel" H 4800 3150 60 0001 C CNN
1 4800 3150
1 0 0 -1
$EndComp
$Comp
L 8:10-CARD P1
U 1 1 4D4702F7
P 8350 5450
F 0 "P1" H 8150 6000 60 0000 C CNN
F 1 "8:10-CARD" H 8400 4850 60 0000 C CNN
F 2 "8:10-card" H 8350 5450 60 0001 C CNN
1 8350 5450
1 0 0 -1
$EndComp
$EndSCHEMATC